Yvan Tortorella
d8972b0f0c
Change L2 address.
2024-04-23 13:58:55 +02:00
Riccardo Tedeschi
f208e9f304
Reduce number of cluster cores for Astral
2024-03-29 10:49:25 +01:00
Yvan Tortorella
54a233a835
Add dedicated astral config.
2024-03-23 19:36:22 +01:00
Riccardo Tedeschi
5c38feaf15
Fix offset in scrubber APIs
2024-02-29 11:46:41 +01:00
Yvan Tortorella
1cbf59cba8
Add APIs for TCDM scrubber.
2024-02-27 19:31:55 +01:00
Yvan Tortorella
90a189ed48
Make DMR regression work on standalone PULP cluster.
2023-10-30 22:15:17 +01:00
Yvan Tortorella
ff4921f39f
Added function to write in the cluster internal return value.
2023-10-20 00:10:38 +02:00
Yvan Tortorella
45de393f94
Set cluster base address properly.
2023-10-06 16:24:45 +02:00
Yvan Tortorella
89fe257eb9
Added code for HMR.
2023-10-03 22:01:45 +02:00
Yvan Tortorella
8acf75d077
Aligned standard out with Carfield.
2023-10-03 13:09:31 +02:00
Yvan Tortorella
f90f2e6343
Shifting up SDTOUT to allow printf in Carfield configuration (to be
...
adjusted with Carfield memory map).
2023-09-30 08:51:45 +02:00
Yvan Tortorella
464d55d260
Fixed runtime issues and masked the cluster ID if the chip is carfield.
2023-08-11 18:56:27 +02:00
Yvan Tortorella
74d44825ed
Fixup: L2 addresses in memory map.
2023-07-12 08:15:03 +02:00
Yvan Tortorella
951a849cce
Added carfield-cluster target and remote function to write eoc.
2023-07-11 19:38:37 +02:00
Yvan Tortorella
138d8e3568
Bumped number of cores to 12.
2023-06-26 15:43:16 +02:00
Yvan Tortorella
968f04e35a
Making a single cluster with non-zero index successfully work.
2023-06-23 19:02:59 +02:00
Yvan Tortorella
2302536715
Enabled traces for debugging (at least in allocation functions).
2023-06-16 11:09:32 +02:00
Luca Valente
41b428de62
Add target pulp_cluster to test the cluster alone.
2023-04-11 19:25:54 +02:00
bluew
1ddf10447c
Merge branch 'control-pulp' into master
2022-06-17 16:03:01 +02:00
bluew
07c26b52ac
pulp-runtime/control-pulp: Use priv_1_12
2022-06-10 18:54:00 +02:00
bluew
7a39de8996
archi: Update privileged level constants
2022-06-10 18:53:40 +02:00
aottaviano
1294f4956b
pulp-runtime: Add idma APIs
...
* Add idma archi and hal sources
* Switch with mchan is still manual
2022-06-01 13:42:02 +02:00
aottaviano
9724be258c
pulp-runtime: Add ARCHI_HAS_DMA_DEMUX property to mchan
...
* If the cluster core demux and peripheral demux have a direct connection
to the dma, allow the cluster cores to use this connection.
2022-06-01 13:41:55 +02:00
aottaviano
77fa6799ed
pulp-runtime: Add kairos target
2022-05-17 08:41:20 +02:00
Corrado Bonfanti
18ab940220
Add AVS BUS support and basic test
...
* Add configuration register to set AVS mode
* Add connections to the SPI controller and txrx interface
* Set idle level of sdio[0] signal of SPI master to '1', according to
the AVS protocol
* Add SPI slave device capability to trigger an event for requesting a read from
master by driving low the MISO (SDATA for AVS) when AVS mode is set.
This happens during tx/rx idle phases
* Add basic Write commit/Read test with pulp-runtime. AVS slave is
simulated in tb_avs.sv and tb_avs_fpga.sv.
2022-02-10 20:03:42 +01:00
aottaviano
735f29948c
treewide: Fix I2C slave module and testsuite
...
* Fix wrong signals in RTL hierarchy
* Add I2C slv tb for FPGA wrapper (dump test)
* Add I2C slv tb for ASIC wrapper (irq test)
* Add dump and irq tests
Please enter the commit message for your changes. Lines starting
2021-12-21 09:45:00 +01:00
bluew
0f4e0e588d
pulp-runtime/control-pulp: Fix vector base set and get
...
So that rt_irq_set_fc_vector_base() and co. pick the correct
implemention using csr mtvec.
2021-11-23 11:01:00 +01:00
bluew
026a98d56a
pulp-runtime: Fix uart frequency and bad fll access
...
Control-pulp doesn't have an FLL so we hardcode the frequency domain
values. Furthermore we allow these hardcoded values to change depending
on whether we target the FPGA (zcu102) or rtl sim.
2021-11-04 17:47:57 +01:00
Michael Rogenmoser
b45d16cdd2
Update UDMA configuration in line with pulp-open
2021-09-21 16:51:02 +02:00
bluew
879eb13dbd
hal: Add missing return value
2021-08-10 16:00:56 +02:00
bluew
868a80fdcd
hal/control-pulp: Remove unnecessary camera include
...
We don't have a camera interface in control-pulp.
2021-07-30 16:56:14 +02:00
aottaviano
3829557a94
include/archi: Fixes for I/O in control-pulp
2021-07-25 19:53:51 +02:00
aottaviano
8380fbdc6b
archi: Fix HW Loops encoding for pulp and pulpissimo with cv32e40p
2021-07-20 16:05:02 +02:00
aottaviano
e4fa83f99e
Fix performance counters API
2021-07-20 16:05:02 +02:00
Luca Valente
8891d83838
target: Add pulp with cv32e40p
2021-07-20 16:04:59 +02:00
Luca Valente
9ad3c4f8d6
hal: Add cpu_perf_start for cv32e40p
2021-07-20 16:04:16 +02:00
Luca Valente
9eba7de59a
target: Add pulpissimo with cv32e40p
2021-07-20 16:03:12 +02:00
aottaviano
eafea63a1e
chips/control_pulp: Overhaul header inclusion for control_pulp
2021-07-19 12:14:04 +02:00
bluew
768f79d507
Add support for control-pulp
2021-07-13 17:33:01 +02:00
bluew
4cea7f6207
archi,hal: Add udma_hyper
2021-07-13 17:33:00 +02:00
bluew
b9fd4bdb7e
hal: Add apb_soc_v4
2021-07-13 17:33:00 +02:00
bluew
f38fa52b54
archi,hal: Add soc_eu_v3
2021-07-13 17:33:00 +02:00
Manuel Eggimann
763fa6f72b
Add SOC_FREQUENCY to fpga specific runtime configuration
2021-06-24 22:01:49 +02:00
Michael Rogenmoser
2ba1be662d
Update Macro naming
2021-02-02 11:09:28 +01:00
Michael Rogenmoser
a907bd73bd
fix ri5cy compatibility
2021-01-22 21:11:35 +01:00
Michael Rogenmoser
babf8b1c4e
Add ibex compatibility to pulpissimo
2021-01-22 17:52:42 +01:00
Michael Rogenmoser
a3f57b07d3
Ibex cleanup
2021-01-04 14:09:11 +01:00
Michael Rogenmoser
c3cfcb45e4
Add ibex performance counters
2021-01-04 11:38:39 +01:00
Michael Rogenmoser
5c9907fd7b
Update ibex irq registers
2020-12-07 09:41:29 +01:00
Michael Rogenmoser
034558d689
change spr_read and write from __builtin to hal for irq
2020-12-07 09:40:15 +01:00
