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fix ri5cy compatibility

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This commit is contained in:
Michael Rogenmoser 2021-01-22 21:11:35 +01:00
parent babf8b1c4e
commit a907bd73bd
2 changed files with 4 additions and 4 deletions
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4
include/bench/bench.h
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@ -174,9 +174,9 @@ static inline void perf_stop(void) {
*/
static inline void perf_reset(void) {
#ifdef CSR_PCER_ALL_EVENTS_MASK
cpu_perf_stop();
perf_stop();
cpu_perf_setall(0);
cpu_perf_start();
perf_start();
#endif
// TODO this is failing on most targets, please include that also for specific ones
#if 0

4
include/hal/riscv/riscv_v5.h
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@ -336,9 +336,9 @@ static inline void cpu_perf_start(unsigned int conf) {
/* Stops counting in all counters. As this is using the mode register,
* the rest of the config can be given through conf parameter */
static inline void cpu_perf_stop(unsigned int conf) {
static inline void cpu_perf_stop() {
#ifndef PLP_NO_PERF_COUNTERS
cpu_perf_conf(conf); // TODO
cpu_perf_conf(0); // TODO
#endif
}