From a907bd73bde2d45e0627c9f71e07c0ea8137142b Mon Sep 17 00:00:00 2001
From: Michael Rogenmoser <michael@rogenmoser.us>
Date: Fri, 22 Jan 2021 21:11:35 +0100
Subject: [PATCH] fix ri5cy compatibility

---
 include/bench/bench.h        | 4 ++--
 include/hal/riscv/riscv_v5.h | 4 ++--
 2 files changed, 4 insertions(+), 4 deletions(-)

diff --git a/include/bench/bench.h b/include/bench/bench.h
index 429012f..dfdd46b 100755
--- a/include/bench/bench.h
+++ b/include/bench/bench.h
@@ -174,9 +174,9 @@ static inline void perf_stop(void) {
  */
 static inline void perf_reset(void) {
 #ifdef CSR_PCER_ALL_EVENTS_MASK
-  cpu_perf_stop();
+  perf_stop();
   cpu_perf_setall(0);
-  cpu_perf_start();
+  perf_start();
 #endif
   // TODO this is failing on most targets, please include that also for specific ones
 #if 0
diff --git a/include/hal/riscv/riscv_v5.h b/include/hal/riscv/riscv_v5.h
index 074e68f..2749750 100644
--- a/include/hal/riscv/riscv_v5.h
+++ b/include/hal/riscv/riscv_v5.h
@@ -336,9 +336,9 @@ static inline void cpu_perf_start(unsigned int conf) {
 
 /* Stops counting in all counters. As this is using the mode register,
  * the rest of the config can be given through conf parameter */
-static inline void cpu_perf_stop(unsigned int conf) {
+static inline void cpu_perf_stop() {
 #ifndef PLP_NO_PERF_COUNTERS
-  cpu_perf_conf(conf); // TODO
+  cpu_perf_conf(0); // TODO
 #endif
 }