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archi,hal: Add soc_eu_v3

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bluew 2021-07-03 22:11:07 +02:00
parent 04e97f6edd
commit f38fa52b54
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70
include/archi/soc_eu/soc_eu_v3.h Normal file
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/*
* Copyright (C) 2018 ETH Zurich and University of Bologna
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef __ARCHI_SOC_EU_SOC_EU_V3_H__
#define __ARCHI_SOC_EU_SOC_EU_V3_H__
#define SOC_EU_EVENT 0x00
#define SOC_FC_FIRST_MASK 0x10
#define SOC_CL_FIRST_MASK 0x20
#define SOC_PR_FIRST_MASK 0x30
#define SOC_ERR_FIRST_MASK 0x40
#define SOC_TIMER_SEL_HI 0x08
#define SOC_TIMER_SEL_LO 0x0C
// compatibility definitions
#define SOC_FC_MASK_LSB SOC_FC_FIRST_MASK
#define SOC_FC_MASK_MSB (SOC_FC_FIRST_MASK + 0x4)
#define SOC_CL_MASK_LSB SOC_CL_FIRST_MASK
#define SOC_CL_MASK_MSB (SOC_CL_FIRST_MASK + 0x4)
#define SOC_PR_MASK_LSB SOC_PR_FIRST_MASK
#define SOC_PR_MASK_MSB (SOC_PR_FIRST_MASK + 0x4)
#define SOC_EU_EVENT_0 0x1
#define SOC_EU_EVENT_1 0x2
#define SOC_EU_EVENT_2 0x4
#define SOC_EU_EVENT_3 0x8
#define SOC_EU_EVENT_4 0x10
#define SOC_EU_EVENT_5 0x20
#define SOC_EU_EVENT_6 0x40
#define SOC_EU_EVENT_7 0x80
#define SOC_TIMER_SEL_ENABLE_SHIFT 31
#define SOC_TIMER_SEL_EVT_SHIFT 0
#define SOC_TIMER_SEL_EVT_WIDTH 8
#define SOC_TIMER_SEL_EVT_MASK ((~0U) >> (32 - SOC_TIMER_SEL_EVT_WIDTH))
// #define SOC_TIMER_SEL_EVT_MASK 0xff
#define SOC_TIMER_SEL_ENABLE_DISABLED 0
#define SOC_TIMER_SEL_ENABLE_ENABLED 1
#define SOC_TIMER_SEL_ENABLE_DIS (0 << SOC_TIMER_SEL_ENABLE_SHIFT)
#define SOC_TIMER_SEL_ENABLE_ENA (1 << SOC_TIMER_SEL_ENABLE_SHIFT)
#define SOC_TIMER_SEL_EVT_VAL(val) ((val) << SOC_TIMER_SEL_EVT_SHIFT)
// related to XX_FIRST_MASK registers
#define SOC_NB_EVENT_REGS 4
#define SOC_NB_EVENT_TARGETS 3
#define SOC_FC_MASK(x) (SOC_FC_FIRST_MASK + (x)*4)
#define SOC_CL_MASK(x) (SOC_CL_FIRST_MASK + (x)*4)
#define SOC_PR_MASK(x) (SOC_PR_FIRST_MASK + (x)*4)
#define ARCHI_SOC_EVENT_PERIPH_EVT_BASE(periph) ((periph)*ARCHI_SOC_EVENT_UDMA_NB_CHANNEL_EVT)
#endif

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include/hal/soc_eu/soc_eu_v3.h Normal file
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/*
* Copyright (C) 2018 ETH Zurich and University of Bologna
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef __HAL_SOC_EU_SOC_EU_V3_H__
#define __HAL_SOC_EU_SOC_EU_V3_H__
#include "archi/pulp.h"
#include "archi/soc_eu/soc_eu_v3.h"
static inline unsigned int hal_soc_eu_addr(void)
{
return ARCHI_SOC_EU_ADDR;
}
static inline void soc_eu_eventMask_set(unsigned int reg, unsigned int value) {
pulp_write32(ARCHI_SOC_EU_ADDR + reg, value);
}
static inline unsigned int soc_eu_eventMask_get(unsigned int reg) {
return pulp_read32(ARCHI_SOC_EU_ADDR + reg);
}
static inline void soc_eu_eventMask_reset(unsigned int first_reg) {
for (int i=0; i<SOC_NB_EVENT_REGS; i++)
{
soc_eu_eventMask_set(first_reg + i*4, 0xffffffff);
}
}
static inline void soc_eu_eventMask_setEvent(int evt, unsigned int first_reg) {
unsigned int reg = first_reg + (evt / 32 * 4);
evt = evt % 32;
soc_eu_eventMask_set(reg, soc_eu_eventMask_get(reg) & ~(1 << evt));
}
static inline void soc_eu_eventMask_clearEvent(int evt, unsigned int first_reg) {
unsigned int reg = first_reg + (evt / 32 * 4);
evt = evt % 32;
soc_eu_eventMask_set(reg, soc_eu_eventMask_get(reg) | (1 << evt));
}
static inline void soc_eu_fcEventMask_setEvent(int evt) {
soc_eu_eventMask_setEvent(evt, SOC_FC_FIRST_MASK);
}
static inline void soc_eu_prEventMask_setEvent(int evt) {
soc_eu_eventMask_setEvent(evt, SOC_PR_FIRST_MASK);
}
static inline void soc_eu_clEventMask_setEvent(int clusterId, int evt) {
soc_eu_eventMask_setEvent(evt, SOC_CL_FIRST_MASK);
}
static inline void soc_eu_fcEventMask_clearEvent(int evt) {
soc_eu_eventMask_clearEvent(evt, SOC_FC_FIRST_MASK);
}
static inline void soc_eu_prEventMask_clearEvent(int evt) {
soc_eu_eventMask_clearEvent(evt, SOC_PR_FIRST_MASK);
}
static inline void soc_eu_clEventMask_clearEvent(int clusterId, int evt) {
soc_eu_eventMask_clearEvent(evt, SOC_CL_FIRST_MASK);
}
static inline void soc_eu_genEventMask(unsigned int mask) {
pulp_write32(ARCHI_SOC_EU_ADDR + SOC_EU_EVENT, mask);
}
/** \brief Select event to be propagated to timer unit event input.
*
* \param timer_id Choice timer Low (1) or High (0).
* \param mask Value on 8 bit to select the event id to be forwarded to the selected timer.
*/
static inline void soc_eu_selEventTimer(unsigned int timer_id, unsigned int mask) {
pulp_write32 (ARCHI_SOC_EU_ADDR + SOC_TIMER_SEL_HI + timer_id * 4
, (pulp_read32(ARCHI_SOC_EU_ADDR + SOC_TIMER_SEL_HI + timer_id * 4) & ~(SOC_TIMER_SEL_EVT_MASK << SOC_TIMER_SEL_EVT_SHIFT))
| (mask & SOC_TIMER_SEL_EVT_MASK));
}
/** \brief Activation of the event forward to timer feature.
*
* \param timer_id Choice timer Low (1) or High (0).
* \param val Value to enable/disable event forwarding to selected timer.
*/
static inline void soc_eu_setEnableEventTimer(unsigned int timer_id, unsigned int val) {
pulp_write32 (ARCHI_SOC_EU_ADDR + SOC_TIMER_SEL_HI + timer_id * 4
, (pulp_read32(ARCHI_SOC_EU_ADDR + SOC_TIMER_SEL_HI + timer_id * 4) & ~(1 << SOC_TIMER_SEL_ENABLE_SHIFT))
| val);
}
#endif