saymrwulf/pulp-runtime
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pulp-runtime: Fix uart frequency and bad fll access

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Control-pulp doesn't have an FLL so we hardcode the frequency domain
values. Furthermore we allow these hardcoded values to change depending
on whether we target the FPGA (zcu102) or rtl sim.
This commit is contained in:
bluew 2021-11-04 17:47:57 +01:00
parent f87c703ac9
commit 026a98d56a
4 changed files with 29 additions and 16 deletions
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4
configs/control-pulp.sh
View file

@ -13,3 +13,7 @@ else
fi
source $scriptDir/common.sh
export PULPRT_CONFIG_CFLAGS='-DARCHI_ASIC_PER_FREQUENCY=100000000 \
-DARCHI_ASIC_FC_FREQUENCY=100000000 \
-DARCHI_ASIC_CL_FREQUENCY=100000000'

21
configs/fpgas/control-pulp/zcu102.sh Normal file
View file

@ -0,0 +1,21 @@
#!/bin/bash -e
export PULPRT_TARGET=control-pulp
export PULPRUN_TARGET=control-pulp
if [ -n "${ZSH_VERSION:-}" ]; then
DIR="$(readlink -f -- "${(%):-%x}")"
scriptDir="$(dirname $DIR)"
else
scriptDir="$(dirname "$(readlink -f "${BASH_SOURCE[0]}")")"
fi
source $scriptDir/../../common.sh
export PULPRUN_PLATFORM=fpga
export PULPRT_CONFIG_CFLAGS='-DARCHI_FPGA_PER_FREQUENCY=10000000 \
-DARCHI_FPGA_FC_FREQUENCY=20000000 \
-DARCHI_FPGA_CL_FREQUENCY=20000000'
export io=uart

1
include/archi/chips/control-pulp/properties.h
View file

@ -22,7 +22,6 @@
* FPGA
*/
#define ARCHI_FPGA_FREQUENCY 5000000
/*
* MEMORIES

19
kernel/chips/control-pulp/soc.c
View file

@ -19,24 +19,13 @@
void pos_soc_init()
{
#if __PLATFORM__ != ARCHI_PLATFORM_FPGA
pos_fll_constructor();
pos_freq_domains[PI_FREQ_DOMAIN_FC] = pos_fll_init(POS_FLL_FC);
pos_freq_domains[PI_FREQ_DOMAIN_PERIPH] = pos_fll_init(POS_FLL_PERIPH);
pos_freq_domains[PI_FREQ_DOMAIN_CL] = pos_fll_init(POS_FLL_CL);
pos_freq_domains[PI_FREQ_DOMAIN_FC] = ARCHI_ASIC_FC_FREQUENCY;
pos_freq_domains[PI_FREQ_DOMAIN_PERIPH] = ARCHI_ASIC_PER_FREQUENCY;
pos_freq_domains[PI_FREQ_DOMAIN_CL] = ARCHI_ASIC_CL_FREQUENCY;
#else
pos_freq_domains[PI_FREQ_DOMAIN_FC] = ARCHI_FPGA_FC_FREQUENCY;
pos_freq_domains[PI_FREQ_DOMAIN_PERIPH] = ARCHI_FPGA_FREQUENCY;
pos_freq_domains[PI_FREQ_DOMAIN_PERIPH] = ARCHI_FPGA_PER_FREQUENCY;
pos_freq_domains[PI_FREQ_DOMAIN_CL] = ARCHI_FPGA_CL_FREQUENCY;
#endif
}