Fixed runtime issues and masked the cluster ID if the chip is carfield.

include/archi/chips/carfield-cluster/memory_map.h

@@ -80,7 +80,7 @@
 
 #define ARCHI_CLUSTER_ADDR              0x00000000
 #define ARCHI_CLUSTER_SIZE              0x00400000
-#define ARCHI_CLUSTER_GLOBAL_ADDR(cid)  (0x4FC00000 + (cid)*ARCHI_CLUSTER_SIZE)
+#define ARCHI_CLUSTER_GLOBAL_ADDR(cid)  (0x50000000 + (cid)*ARCHI_CLUSTER_SIZE)
 
 
 

include/archi/pulp_defs.h

@@ -70,6 +70,7 @@
 #define CHIP_VIVOSOC4              48
 #define CHIP_WOLFE_16              49
 #define CHIP_MARSELLUS             50
+#define CHIP_CARFIELD              51
 
 #define CORE_OR1K_V1  0
 #define CORE_OR1K_V2  1
@@ -88,4 +89,4 @@
 #define ARCHI_PLATFORM_GVSOC 3
 #define ARCHI_PLATFORM_BOARD 4
 
-#endif
+#endif

include/chips/carfield-cluster/config.h

@@ -19,8 +19,8 @@
 
 #include "archi/pulp_defs.h"
 
-#define PULP_CHIP CHIP_PULP
-#define PULP_CHIP_FAMILY CHIP_PULP
+#define PULP_CHIP CHIP_CARFIELD
+#define PULP_CHIP_FAMILY CHIP_CARFIELD
 #define CONFIG_PULP 1
 #define PULP_CHIP_STR carfield-cluster
 #define PULP_CHIP_FAMILY_STR carfield-cluster

include/data/data.h

@@ -39,7 +39,7 @@
 #define PI_L2 __attribute__((section(".l2_data")))
 #define L2_DATA PI_L2
 
-#define L1_GLOBAL_DATA __attribute__((section("__data_l1")))
+#define L1_GLOBAL_DATA __attribute__((section(".data_l1")))
 #define L1_DATA L1_GLOBAL_DATA
 
 #ifdef USE_CLUSTER

include/hal/cv32e40p/cv32e40p.h

@@ -142,7 +142,11 @@ static inline unsigned int cluster_id() {
   int hart_id;
   asm("csrr %0, 0xF14" : "=r" (hart_id) : );
   // in PULP the hart id is {22'b0, cluster_id, core_id}
+#if PULP_CHIP == CHIP_CARFIELD
+  return (hart_id >> 6);
+#else
   return (hart_id >> 5) & 0x3f;
+#endif
 }
 
 #ifndef PLP_NO_BUILTIN
@@ -188,7 +192,11 @@ static inline __attribute__((always_inline)) unsigned int hal_cluster_id() {
   int hart_id;
   asm("csrr %0, 0xF14" : "=r" (hart_id) : );
   // in PULP the hart id is {22'b0, cluster_id, core_id}
+#if PULP_CHIP == CHIP_CARFIELD
+  return (hart_id >> 6);
+#else
   return (hart_id >> 5) & 0x3f;
+#endif
 }
 
 static inline __attribute__((always_inline)) unsigned int hal_has_fc() {

include/hal/ibex/ibex.h

@@ -86,7 +86,11 @@ static inline unsigned int cluster_id() {
   int hart_id;
   asm("csrr %0, 0xF14" : "=r" (hart_id) : );
   // in PULP the hart id is {22'b0, cluster_id, core_id}
+#if PULP_CHIP == CHIP_CARFIELD
+  return (hart_id >> 6);
+#else
   return (hart_id >> 5) & 0x3f;
+#endif
 }
 
 static inline unsigned int hal_core_id() {

include/hal/riscv/riscv_v5.h

@@ -158,7 +158,11 @@ static inline unsigned int cluster_id() {
   asm("csrr %0, 0xF10" : "=r" (hart_id) : );
 #endif
   // in PULP the hart id is {22'b0, cluster_id, core_id}
+#if PULP_CHIP == CHIP_CARFIELD
+  return (hart_id >> 6);
+#else
   return (hart_id >> 5) & 0x3f;
+#endif
 }
 
 #ifndef PLP_NO_BUILTIN
@@ -220,7 +224,11 @@ static inline __attribute__((always_inline)) unsigned int hal_cluster_id() {
   asm("csrr %0, 0xF10" : "=r" (hart_id) : );
 #endif
   // in PULP the hart id is {22'b0, cluster_id, core_id}
+#if PULP_CHIP == CHIP_CARFIELD
+  return (hart_id >> 6);
+#else
   return (hart_id >> 5) & 0x3f;
+#endif
 }
 
 static inline __attribute__((always_inline)) unsigned int hal_has_fc() {

kernel/chips/carfield-cluster/link.ld

@@ -4,7 +4,7 @@ ENTRY( _start )
 MEMORY
 {
   L2           : ORIGIN = 0x78000000, LENGTH = 0x003FFFFC
-  L1           : ORIGIN = 0x4FC00000, LENGTH = 0x0003FFFC
+  L1           : ORIGIN = 0x50000000, LENGTH = 0x0003FFFC
 }
 
 /*
@@ -180,6 +180,7 @@ SECTIONS
 
   .vectors MAX(0x78008000,ALIGN(256)) :
   {
+    /*. = ALIGN(256);*/
     __irq_vector_base = .;
     KEEP(*(.vectors))
   } > L2
@@ -225,12 +226,10 @@ SECTIONS
 
   .l1cluster_g : {
     . = ALIGN(4);
-    __heap_sram = .;
     *(.heapsram)
     *(.heapsram.*)
     *(.l1cluster_g)
     *(.l1cluster_g.*)
-    __data_l1 = .;
     *(.data_l1)
     *(.data_l1.*)
     . = ALIGN(4);

kernel/crt0.S

@@ -29,7 +29,13 @@ pos_init_entry:
 #ifdef ARCHI_NO_FC
     # PEs from 1 to 7 will go to sync_loop and wait. PE0 will reach them
     # later after the pos_init_start. Then, they'll set up their stack into
-    # the L1 and jump to cluster_entry_stub
+  # the L1 and jump to cluster_entry_stub
+#if PULP_CHIP == CHIP_CARFIELD
+    li t0, 0x5003FFF0
+#else
+    li t0, 0x1003FF0
+#endif
+    sw x0, 0(t0)
     # We check if the offset of the core is zero, so that even if the cluster
     # ID is not zero, the execution does not break here
     andi    a2, a0, 0x0f
@@ -77,6 +83,13 @@ pos_init_entry:
 #ifdef ARCHI_NO_FC
     csrr    a0, 0xF14
     andi    a1, a0, 0x1f
+#if PULP_CHIP == CHIP_CARFIELD
+    li t0, 0x5003FFF0
+#else
+    li t0, 0x1003FFF0
+#endif
+    li t1, 0x1
+    sw t1, 0(t0)
     j pe_start
 #endif
 

rules/pulpos/targets/carfield-cluster.mk

@@ -22,10 +22,12 @@ PULP_CFLAGS    += -fdata-sections -ffunction-sections -include chips/carfield-cl
 PULP_OMP_CFLAGS    += -fopenmp -mnativeomp
 PULP_LDFLAGS += -nostartfiles -nostdlib -Wl,--gc-sections -L$(PULPRT_HOME)/kernel -Tchips/carfield-cluster/link.ld -lgcc
 
-PULP_CC = riscv32-unknown-elf-gcc
-PULP_AR ?= riscv32-unknown-elf-ar
-PULP_LD ?= riscv32-unknown-elf-gcc
-PULP_OBJDUMP ?= riscv32-unknown-elf-objdump
+PULPD_RISCV ?= riscv32-unknown-elf
+
+PULP_CC ?= $(PULPD_RISCV)-gcc
+PULP_AR ?= $(PULPD_RISCV)-ar
+PULP_LD ?= $(PULPD_RISCV)-gcc
+PULP_OBJDUMP ?= $(PULPD_RISCV)-objdump
 
 fc/archi=riscv
 pe/archi=riscv