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Update Macro naming
This commit is contained in:
Michael Rogenmoser
parent
a907bd73bd
commit
2ba1be662d
1 changed files with 34 additions and 34 deletions
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@ -19,45 +19,45 @@
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/*
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* Bit definitions for Performance counters mode registers
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*
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* (see https://ibex-core.readthedocs.io/en/latest/03_reference/performance_counters.html)
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*/
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#define IBEX_MHPMCOUNTER_BASE 0xB00
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// Currently the additional register for more perf. counting is not yet implemented
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// ibex performance counters
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#define IBEX_NumCycles 0 /* Number of cycles */
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#define IBEX_NumInstrRet 2 /* Number of instructions retired */
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#define IBEX_NumCyclesLSU 3 /* Number of cycles waiting for data memory */
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#define IBEX_NumCyclesIF 4 /* Cycles waiting for instruction fetches, i.e., number of instructions wasted due to non-ideal caching */
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#define IBEX_NumLoads 5 /* Number of data memory loads. Misaligned accesses are counted as two accesses */
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#define IBEX_NumStores 6 /* Number of data memory stores. Misaligned accesses are counted as two accesses */
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#define IBEX_NumJumps 7 /* Number of unconditional jumps (j, jal, jr, jalr) */
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#define IBEX_NumBranches 8 /* Number of branches (conditional) */
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#define IBEX_NumBranchesTaken 9 /* Number of taken branches (conditional) */
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#define IBEX_NumInstrRetC 10 /* Number of compressed instructions retired */
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#define IBEX_NumCyclesMulWait 11 /* Cycles waiting for multiply to complete */
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#define IBEX_NumCyclesDivWait 12 /* Cycles waiting for divide to complete */
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#define IBEX_NUM_CYCLES 0 /* NumCycles: Number of cycles */
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#define IBEX_NUM_INSTR_RET 2 /* NumInstrRet: Number of instructions retired */
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#define IBEX_NUM_CYCLES_LSU 3 /* NumCyclesLSU: Number of cycles waiting for data memory */
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#define IBEX_NUM_CYCLES_IF 4 /* NumCyclesIF: Cycles waiting for instruction fetches, i.e., number of instructions wasted due to non-ideal caching */
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#define IBEX_NUM_LOADS 5 /* NumLoads: Number of data memory loads. Misaligned accesses are counted as two accesses */
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#define IBEX_NUM_STORES 6 /* NumStores: Number of data memory stores. Misaligned accesses are counted as two accesses */
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#define IBEX_NUM_JUMPS 7 /* NumJumps: Number of unconditional jumps (j, jal, jr, jalr) */
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#define IBEX_NUM_BRANCHES 8 /* NumBranches: Number of branches (conditional) */
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#define IBEX_NUM_BRANCHES_TAKEN 9 /* NumBranchesTaken: Number of taken branches (conditional) */
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#define IBEX_NUM_INSTR_RET_C 10 /* NumInstrRetC: Number of compressed instructions retired */
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#define IBEX_NUM_CYCLES_MUL_WAIT 11 /* NumCyclesMulWait: Cycles waiting for multiply to complete */
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#define IBEX_NUM_CYCLES_DIV_WAIT 12 /* NumCyclesDivWait: Cycles waiting for divide to complete */
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// riscv map for ibex counters
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#define CSR_PCER_CYCLES IBEX_NumCycles /* Count the number of cycles the core was running */
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#define CSR_PCER_INSTR IBEX_NumInstrRet /* Count the number of instructions executed */
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#define CSR_PCER_LD_STALL IBEX_NumCyclesLSU /* Number of load use hazards */
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#define CSR_PCER_IMISS IBEX_NumCyclesIF /* Cycles waiting for instruction fetches. i.e. the number of instructions wasted due to non-ideal caches */
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#define CSR_PCER_LD IBEX_NumLoads /* Number of memory loads executed. Misaligned accesses are counted twice */
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#define CSR_PCER_ST IBEX_NumStores /* Number of memory stores executed. Misaligned accesses are counted twice */
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#define CSR_PCER_JUMP IBEX_NumJumps /* Number of jump instructions seen, i.e. j, jr, jal, jalr */
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#define CSR_PCER_BRANCH IBEX_NumBranches /* Number of branch instructions seen, i.e. bf, bnf */
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#define CSR_PCER_TAKEN_BRANCH IBEX_NumBranchesTaken /* Number of taken branch instructions seen, i.e. bf, bnf */
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#define CSR_PCER_RVC IBEX_NumInstrRetC /* Number of compressed instructions */
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#define CSR_PCER_CYCLES IBEX_NUM_CYCLES /* Count the number of cycles the core was running */
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#define CSR_PCER_INSTR IBEX_NUM_INSTR_RET /* Count the number of instructions executed */
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#define CSR_PCER_LD_STALL IBEX_NUM_CYCLES_LSU /* Number of load use hazards */
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#define CSR_PCER_IMISS IBEX_NUM_CYCLES_IF /* Cycles waiting for instruction fetches. i.e. the number of instructions wasted due to non-ideal caches */
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#define CSR_PCER_LD IBEX_NUM_LOADS /* Number of memory loads executed. Misaligned accesses are counted twice */
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#define CSR_PCER_ST IBEX_NUM_STORES /* Number of memory stores executed. Misaligned accesses are counted twice */
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#define CSR_PCER_JUMP IBEX_NUM_JUMPS /* Number of jump instructions seen, i.e. j, jr, jal, jalr */
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#define CSR_PCER_BRANCH IBEX_NUM_BRANCHES /* Number of branch instructions seen, i.e. bf, bnf */
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#define CSR_PCER_TAKEN_BRANCH IBEX_NUM_BRANCHES_TAKEN /* Number of taken branch instructions seen, i.e. bf, bnf */
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#define CSR_PCER_RVC IBEX_NUM_INSTR_RET_C /* Number of compressed instructions */
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// Not implemented in ibex
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// #define CSR_PCER_ELW 0 /* Cycles wasted due to ELW instruction */
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// #define CSR_PCER_JMP_STALL 0 /* Number of jump register hazards */
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// External perf counters
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#define IBEX_External_BASE 13
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#define IBEX_EXTERNAL_BASE 13
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#define CSR_PCER_LD_EXT 13 /* Number of memory loads to EXT executed. Misaligned accesses are counted twice. Every non-TCDM access is considered external */
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#define CSR_PCER_ST_EXT 14 /* Number of memory stores to EXT executed. Misaligned accesses are counted twice. Every non-TCDM access is considered external */
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#define CSR_PCER_LD_EXT_CYC 15 /* Cycles used for memory loads to EXT. Every non-TCDM access is considered external */
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@ -76,16 +76,16 @@
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#define CSR_PCER_ALL_EVENTS_MASK 0xffffffff
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#define CSR_PCER_NAME(id) \
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( id == IBEX_NumCycles ? "Cycles" : \
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id == IBEX_NumInstrRet ? "Instructions" : \
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id == IBEX_NumCyclesLSU ? "LD_Stall" : \
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id == IBEX_NumCyclesIF ? "IMISS" : \
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id == IBEX_NumLoads ? "LD" : \
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id == IBEX_NumStores ? "ST" : \
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id == IBEX_NumJumps ? "JUMP" : \
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id == IBEX_NumBranches ? "BRANCH" : \
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id == IBEX_NumBranchesTaken ? "TAKEN_BRANCH" : \
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id == IBEX_NumInstrRetC ? "RVC" : \
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( id == IBEX_NUM_CYCLES ? "Cycles" : \
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id == IBEX_NUM_INSTR_RET ? "Instructions" : \
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id == IBEX_NUM_CYCLES_LSU ? "LD_Stall" : \
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id == IBEX_NUM_CYCLES_IF ? "IMISS" : \
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id == IBEX_NUM_LOADS ? "LD" : \
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id == IBEX_NUM_STORES ? "ST" : \
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id == IBEX_NUM_JUMPS ? "JUMP" : \
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id == IBEX_NUM_BRANCHES ? "BRANCH" : \
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id == IBEX_NUM_BRANCHES_TAKEN ? "TAKEN_BRANCH" : \
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id == IBEX_NUM_INSTR_RET_C ? "RVC" : \
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id == 16 ? "LD_EXT" : \
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id == 17 ? "ST_EXT" : \
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id == 18 ? "LD_EXT_CYC" : \
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