From 2ba1be662d86ac1e783faf16720b02bad18fb38e Mon Sep 17 00:00:00 2001 From: Michael Rogenmoser Date: Tue, 2 Feb 2021 11:09:28 +0100 Subject: [PATCH] Update Macro naming --- include/archi/ibex/mhpm.h | 68 +++++++++++++++++++-------------------- 1 file changed, 34 insertions(+), 34 deletions(-) diff --git a/include/archi/ibex/mhpm.h b/include/archi/ibex/mhpm.h index 5520e47..a581442 100644 --- a/include/archi/ibex/mhpm.h +++ b/include/archi/ibex/mhpm.h @@ -19,45 +19,45 @@ /* * Bit definitions for Performance counters mode registers - * + * (see https://ibex-core.readthedocs.io/en/latest/03_reference/performance_counters.html) */ #define IBEX_MHPMCOUNTER_BASE 0xB00 // Currently the additional register for more perf. counting is not yet implemented // ibex performance counters -#define IBEX_NumCycles 0 /* Number of cycles */ -#define IBEX_NumInstrRet 2 /* Number of instructions retired */ -#define IBEX_NumCyclesLSU 3 /* Number of cycles waiting for data memory */ -#define IBEX_NumCyclesIF 4 /* Cycles waiting for instruction fetches, i.e., number of instructions wasted due to non-ideal caching */ -#define IBEX_NumLoads 5 /* Number of data memory loads. Misaligned accesses are counted as two accesses */ -#define IBEX_NumStores 6 /* Number of data memory stores. Misaligned accesses are counted as two accesses */ -#define IBEX_NumJumps 7 /* Number of unconditional jumps (j, jal, jr, jalr) */ -#define IBEX_NumBranches 8 /* Number of branches (conditional) */ -#define IBEX_NumBranchesTaken 9 /* Number of taken branches (conditional) */ -#define IBEX_NumInstrRetC 10 /* Number of compressed instructions retired */ -#define IBEX_NumCyclesMulWait 11 /* Cycles waiting for multiply to complete */ -#define IBEX_NumCyclesDivWait 12 /* Cycles waiting for divide to complete */ +#define IBEX_NUM_CYCLES 0 /* NumCycles: Number of cycles */ +#define IBEX_NUM_INSTR_RET 2 /* NumInstrRet: Number of instructions retired */ +#define IBEX_NUM_CYCLES_LSU 3 /* NumCyclesLSU: Number of cycles waiting for data memory */ +#define IBEX_NUM_CYCLES_IF 4 /* NumCyclesIF: Cycles waiting for instruction fetches, i.e., number of instructions wasted due to non-ideal caching */ +#define IBEX_NUM_LOADS 5 /* NumLoads: Number of data memory loads. Misaligned accesses are counted as two accesses */ +#define IBEX_NUM_STORES 6 /* NumStores: Number of data memory stores. Misaligned accesses are counted as two accesses */ +#define IBEX_NUM_JUMPS 7 /* NumJumps: Number of unconditional jumps (j, jal, jr, jalr) */ +#define IBEX_NUM_BRANCHES 8 /* NumBranches: Number of branches (conditional) */ +#define IBEX_NUM_BRANCHES_TAKEN 9 /* NumBranchesTaken: Number of taken branches (conditional) */ +#define IBEX_NUM_INSTR_RET_C 10 /* NumInstrRetC: Number of compressed instructions retired */ +#define IBEX_NUM_CYCLES_MUL_WAIT 11 /* NumCyclesMulWait: Cycles waiting for multiply to complete */ +#define IBEX_NUM_CYCLES_DIV_WAIT 12 /* NumCyclesDivWait: Cycles waiting for divide to complete */ // riscv map for ibex counters -#define CSR_PCER_CYCLES IBEX_NumCycles /* Count the number of cycles the core was running */ -#define CSR_PCER_INSTR IBEX_NumInstrRet /* Count the number of instructions executed */ -#define CSR_PCER_LD_STALL IBEX_NumCyclesLSU /* Number of load use hazards */ -#define CSR_PCER_IMISS IBEX_NumCyclesIF /* Cycles waiting for instruction fetches. i.e. the number of instructions wasted due to non-ideal caches */ -#define CSR_PCER_LD IBEX_NumLoads /* Number of memory loads executed. Misaligned accesses are counted twice */ -#define CSR_PCER_ST IBEX_NumStores /* Number of memory stores executed. Misaligned accesses are counted twice */ -#define CSR_PCER_JUMP IBEX_NumJumps /* Number of jump instructions seen, i.e. j, jr, jal, jalr */ -#define CSR_PCER_BRANCH IBEX_NumBranches /* Number of branch instructions seen, i.e. bf, bnf */ -#define CSR_PCER_TAKEN_BRANCH IBEX_NumBranchesTaken /* Number of taken branch instructions seen, i.e. bf, bnf */ -#define CSR_PCER_RVC IBEX_NumInstrRetC /* Number of compressed instructions */ +#define CSR_PCER_CYCLES IBEX_NUM_CYCLES /* Count the number of cycles the core was running */ +#define CSR_PCER_INSTR IBEX_NUM_INSTR_RET /* Count the number of instructions executed */ +#define CSR_PCER_LD_STALL IBEX_NUM_CYCLES_LSU /* Number of load use hazards */ +#define CSR_PCER_IMISS IBEX_NUM_CYCLES_IF /* Cycles waiting for instruction fetches. i.e. the number of instructions wasted due to non-ideal caches */ +#define CSR_PCER_LD IBEX_NUM_LOADS /* Number of memory loads executed. Misaligned accesses are counted twice */ +#define CSR_PCER_ST IBEX_NUM_STORES /* Number of memory stores executed. Misaligned accesses are counted twice */ +#define CSR_PCER_JUMP IBEX_NUM_JUMPS /* Number of jump instructions seen, i.e. j, jr, jal, jalr */ +#define CSR_PCER_BRANCH IBEX_NUM_BRANCHES /* Number of branch instructions seen, i.e. bf, bnf */ +#define CSR_PCER_TAKEN_BRANCH IBEX_NUM_BRANCHES_TAKEN /* Number of taken branch instructions seen, i.e. bf, bnf */ +#define CSR_PCER_RVC IBEX_NUM_INSTR_RET_C /* Number of compressed instructions */ // Not implemented in ibex // #define CSR_PCER_ELW 0 /* Cycles wasted due to ELW instruction */ // #define CSR_PCER_JMP_STALL 0 /* Number of jump register hazards */ // External perf counters -#define IBEX_External_BASE 13 +#define IBEX_EXTERNAL_BASE 13 #define CSR_PCER_LD_EXT 13 /* Number of memory loads to EXT executed. Misaligned accesses are counted twice. Every non-TCDM access is considered external */ #define CSR_PCER_ST_EXT 14 /* Number of memory stores to EXT executed. Misaligned accesses are counted twice. Every non-TCDM access is considered external */ #define CSR_PCER_LD_EXT_CYC 15 /* Cycles used for memory loads to EXT. Every non-TCDM access is considered external */ @@ -76,16 +76,16 @@ #define CSR_PCER_ALL_EVENTS_MASK 0xffffffff #define CSR_PCER_NAME(id) \ - ( id == IBEX_NumCycles ? "Cycles" : \ - id == IBEX_NumInstrRet ? "Instructions" : \ - id == IBEX_NumCyclesLSU ? "LD_Stall" : \ - id == IBEX_NumCyclesIF ? "IMISS" : \ - id == IBEX_NumLoads ? "LD" : \ - id == IBEX_NumStores ? "ST" : \ - id == IBEX_NumJumps ? "JUMP" : \ - id == IBEX_NumBranches ? "BRANCH" : \ - id == IBEX_NumBranchesTaken ? "TAKEN_BRANCH" : \ - id == IBEX_NumInstrRetC ? "RVC" : \ + ( id == IBEX_NUM_CYCLES ? "Cycles" : \ + id == IBEX_NUM_INSTR_RET ? "Instructions" : \ + id == IBEX_NUM_CYCLES_LSU ? "LD_Stall" : \ + id == IBEX_NUM_CYCLES_IF ? "IMISS" : \ + id == IBEX_NUM_LOADS ? "LD" : \ + id == IBEX_NUM_STORES ? "ST" : \ + id == IBEX_NUM_JUMPS ? "JUMP" : \ + id == IBEX_NUM_BRANCHES ? "BRANCH" : \ + id == IBEX_NUM_BRANCHES_TAKEN ? "TAKEN_BRANCH" : \ + id == IBEX_NUM_INSTR_RET_C ? "RVC" : \ id == 16 ? "LD_EXT" : \ id == 17 ? "ST_EXT" : \ id == 18 ? "LD_EXT_CYC" : \