When running
$ n3xx_bist ddr3
The test will now load the AA image if the BIST fails, unless the user
specifies
$ n3xx_bist ddr3 -o skip_load_fpga=1
The rationale is that by default, the AA image is the only one that
includes the DmaFIFO block.
The capability to run the DDR3 BIST is built into the DmaFIFO RFNoC
block, which is not always available. This change performs a quick check
before for its existence before retrieving the throughput values, and
thus can provide a better error message in that case.
We can't guarantee that there is actually a DDR3/DRAM FIFO block on the
image. So, don't run that test by default.
In order to run the DDR3 bist, running `n3xx_bist ddr3` is still valid.
However, it requires an image with the DRAM FIFO enabled.
Without this patch, the N320 code will rely on an error to occur to
determine the non-existence of the N321 LO distribution board. While
this works, it forces an error message where there's no error. This will
first check for the existence of the board before trying to initialize
it.
Issue: Current code loads FPGA too early while many
essential peripherals such as net clocks are not brought up.
This change will make sure those are got init before FPGA loaded.
Signed-off-by: Trung Tran<trung.tran@ettus.com>
Add an argument to the UDP xport_mgr to adjust the xport sorting. This
enables Rhodium to use a different limit from Magnesium. Previously, the
sorting method would overload a link with both of Rhodium's higher-rate
streams.
Fixes Rhodium for changes introduced in b7bab6a. The constructor call
for BfrfsEEPROM didn't match the signature, and Rhodium's EEPROM map
referred to the wrong revision.
Add method to generate GPGGA sensor data in MPM devices. This needs to
be constructed from TPV and SKY sensor data, and matches the GPGGA
sensor functionality in gpsd_iface.cpp.
Previously, the init() procedure of the n3xx class passed either
the user-provided or the default clock_source and time_source values
to initialize the clocking configuration.
When the user did not provide these parameters, the default values
were assigned, overriding whatever configuration the device was
previously initialized with. Therefore, a dboard reinit was forced
when the currently configured state of the N3xx device did not match
the default configuration (i.e. internal sources).
Now, the init() procedure still provides the clock_source and
time_source values; but, if the user does not provide the
parameters, the previously used values are assigned (i.e.
self._clock_source and/or self._time_source).
By the time MPM runs this n3xx init() procedure for the first time,
both self._clock_source and self._time_source have been initialized
with the default internal values anyways in the
_init_ref_clock_and_time() procedure.
This change prevents additional, unnecessary calls to the
set_sync_source() procedure, which ultimately causes a daughterboard
reinitialization when either a new clock or time source is requested.
The update_ref_clock_freq() procedure now updates the self._init_args
value of the Rhodium class daugtherboard objects in MPM to propagate
the latest user-selected arguments for future reference.
gpsd connection is not reliable.
Adding more error handling to re-connect during polling.
Add control flows to get_gps_time in order to give an effect of getting
the value on pps edge.
- This is a combination of 5 commits.
- rh: add lo distribution board gpio expander
- rh: add lo distribution mpm functions
- rh: add code to conditionally initialize lo distribution
- rh: change empty i2c device from exception to assertion
- rh: add lo distribution board control
- Confirmed the Phase DAC to be initialized at mid-scale.
- Confirmed the Phase DAC step resolution for fine clock shifting.
The clock synchronization algorithm relies on the Phase DAC to fine
shift the sampling clocks on each daughterboard.
Only a certain number of DAC codes are required for the actual clock
adjustment, thus a different range of codes may be chosen by
initializing the Phase DAC with a given value. With the selected range,
one may measure the Phase DAC's linearity and step resolution, which
defines how many steps are required when performing the fine shifting
of the clocks.
After initializing the 16-bit Phase DAC at 25%, 50% (mid-scale), and
75%; it was found that the clock distribution PLL locks relatively
faster when using mid-scale (2^15). By testing the Phase DAC's
linearity, it was confirmed that the circuit resolution is 1.11 ps per
code.
- Optimized JESD204B RX/TX links' latency.
- Made JESD latency constant across supported frequencies.
- Checking RX SYSREF capture in the FPGA deframer block.
The JESD204B standard can be linked in such a way to produce a
repeatable, deterministic delay from the framer to deframer. This is
accomplished by setting up a LMFC (local multiframe clock) in both
devices.
The LMFCs are reset whenever a SYSREF edge is captured by the framer
and deframer. Therefore, it is simple to control the LMFC rising edges
in each device by implementing variable delay elements on the SYSREF
pulses to the framer and deframer.
Latency across the JESD204B TX/RX links should remain constant and
deterministic across the supported sampling_clock_rate values. By
testing the roundtrip latency (i.e. FPGA -> TX -> RX -> FPGA) with
different delay values in the FPGA, one may decrease the latency and
provide enough setup and hold margin for the data to be transfered
through each JESD link.
It was found that a different set of SYSREF delay values are required
for sampling_clock_rate = 400 MSPS to match the latency of the other
supported rates.
Add coercing behavior to set_time_source and set_clock_source to
a valid sync source. Also, skip set_sync_source if device already
set to the corresponding one.
Summary:
This change will allow correct args to pass from mboard to dboards,
that in turn can be useful for dboard manager.
Details:
In N310, the dboard manager needs the time source to be updated before
calling update_ref_clock_source(), because it will trigger a reinit of
the dboard, for which the time_source is essential to determine correct
clock synchronizer settings.
The special case is the white rabbit time source needs a different
internal ref_clock_frequency for the clock synchronizer than the passed
in ref_clock_freq.
This provides a new utility for MPM devices (usrp_update_fs.py), which
goes through all the necessary steps to update a filesystem.
Will trigger a mender update, but the tool is not specific to Mender
and can be changed to use other methods in the future.
When reloading the Periph Manager (as when we run the image loader),
we need to run the RPCServer `__init__` function in order to reset the
cache of RPC methods. Otherwise, that cache keeps stale references to
old functions (and prevents garbage collection).
It may be possible to reset the method cache some other way, but the
`_methods` attribute of RPCServer is Cython, and doesn't seem to be
accessible in our Python code.
Adding MPM Git hash and version to the MPM device info. This
information is currently only available through logs when MPM starts
(it is the first log message in usrp_hwd.py). Adding it to the device
info makes it accessible to any application which checks that, such as
uhd_usrp_probe.
- For different ref clock frequencies, the ref_counter should change
and not the n_counter.
- The charge pump should be set to normal mode and tristate as that
would prevent the PLL to lock.
- ref_clock_(int/ext) test was not changing adf400x driver settings
for new ref clock frequency. Therefore, changed the implementation
to use uhd_usrp_probe --sensor to set clock_source and get
'ref_locked' sensor value
Added set_sync_source method to set both the time and clock sources
without forcing a re-init twice. Modified the existing set_time_source
and set_clock_source methods to call into set_sync_source.
EEPROM parsing in MPM was ignoring the dt_compat number (MPM doesn't
need it), so when the dt_compat number was non-zero, the CRC
calculation was incorrect. CRC calculations are now done on the raw
data.
- Fix the syntax to open mboard-regs UIO objects, and change the open()
and close() functions to be private.
- We were calling open() twice in every context manager line- once
manually, and once in __enter__. This commit corrects those usages, and
allows the context manager to fully manage the opening and closing of
UIO objects.
The tests for white rabbit and SFP loopback require a specific FPGA
image. We now check if that image is already available before running
uhd_image_loader.
Adding the following sensors:
- Catalina temperature, RSSI, and LO Lock sensors
- GPS lock, time, TPV, and SKY sensors
Co-authored-by: Brent Stapleton <brent.stapleton@ettus.com>
When a device is re-initialized without any changes (e.g.,
master_clock_rate, ref_clock_freq) then we can skip the initialization
sequence and move on. This shaves a significant amount of time from the
init sequence.
Fast re-init can be overridden by providing the `force_reinit=1` device
arg.
- Refactoring component (FPGA, DTS) updating functions out of
n3xx.py into their own components.py. The ZynqComponent class now
defines the methods to update these two components.
- Adding super().__init__() to the PeriphManagerBase class. This is
needed to get the multiple inheritance used in N3XX now to work, and
(apparently) good Python practice.
- Refactoring GPSd interface to be instead wrapped by a
GPSDIfaceExtension class. This class will faciliate "extending" an
object, allowing that object to call the GPSDIfaceExtension methods as
their own.
- New MPM devices (or whatever else) can now use the GPSDIfaceExtension
class instead of writing their own GPSDIface handling functions.
- N3XX now instantiates a GPSDIfaceExtension object, and extends
itself. This means that an n3xx object can call the `get_gps_time`
method as its own, for example.
- N3XX must get through initialization in order for the GPSd methods
to be registered.
Moving the RFNoC crossbar base port to the class overridables. MPM
devices may need to reserve different numbers of ports for non-blocks;
this can now be done by overriding the crossbar_base_port.
Introduce dt-compat and mcu-compat fields into the eeprom
structure.
For the motherboard eeprom this is straightforward, since
there's still padding bytes that could be (ab)used for this.
On the dboard side more creativity is required and the
original revision field of 2 bytes is reduced to only
one byte revision and one byte dt-compat.
Since this will only affect new units being backwards
compatible with older versions of the bootloader is not
an issue.
Reviewed-by: Brent Stapleton <brent.stapleton@ettus.com>
Signed-off-by: Moritz Fischer <moritz.fischer@ettus.com>
This manager first detects all valid Ethernet devices. The checks for
validity happen across multiple calls in a non-atomic fashion, so it's
possible to end up with inconsistent results. To avoid such issues, we
filter results without talking to the network stack as a final pass.
Because the detection of valid Ethernet devices happens across multiple
calls in a non-atomic fashion, we cannot assume that a device passed to
net.get_iface_info() actually has a valid IP address, so we don't make
that assumption.
Since there is no simple mapping from an arbitrary tuple of mboard- and
dboard info dictionaries, we use generate_device_info() to figure out
the product key.
In the N3xx series, the motherboard ID and the device ID can differ. For
example, the N310 could share the same motherboard with a different
device that uses different daughterboards.
This changes the sorting algorithm for the xport<->SFP mapping. When
multiple SFPs are used, this sorting will avoid a criss-cross mapping
(e.g., mapping ports 0 and 1 of 0/Radio_0 to different SFPs).
- Replace mykonos finish_initialization with async version
- Replace myknonos setup_cal with async version
- Remove disable_timeout on rpc_server init()
Usually, the current timeout is fine, but there are cases when a lot of
RPC traffic could drown out the reclaim calls. 5 seconds is an
experimentally derived safe value.
Separating Boost.Python bindings into device-specific files. N3XX code
now lives in n3xx/pyusrp_periphs. Only one src file should be added for
pyusrp_periphs.so by CMake.
Bump maximum supported motherboard revision to 5 (RevF),
to support upcoming motherboard revisions.
Signed-off-by: Moritz Fischer <moritz.fischer@ettus.com>
Adding address offset to all MBoard and DBoard EEPROM reads. This
matches what we're doing for the user portion of the EEPROM, and
allows us to share access to an EEPROM.
UIO objects now count references on open and close calls. This should
prevent problems with nested function calls that open/close the same
UIO object.
References counts are not atomic -- this is intended for nesting with
statements within the same thread context.
Reviewed-by: Martin Braun <martin.braun@ettus.com>
Reviewed-by: Trung Tran <trung.tran@ettus.com>
The log output at level 'INFO' was pretty cluttered. This cleans up the
log messages at the higher levels. In some cases, log message typos or
capitalizations were also fixed.
The FPGA and MPM version as well as the description of the device
("N300-Series Device") and its name (its the hostname) are now properly
reported coming from MPM, properly saved in the prop tree, and
uhd_usrp_probe can nicely display them this way.
