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- Confirmed the Phase DAC to be initialized at mid-scale. - Confirmed the Phase DAC step resolution for fine clock shifting. The clock synchronization algorithm relies on the Phase DAC to fine shift the sampling clocks on each daughterboard. Only a certain number of DAC codes are required for the actual clock adjustment, thus a different range of codes may be chosen by initializing the Phase DAC with a given value. With the selected range, one may measure the Phase DAC's linearity and step resolution, which defines how many steps are required when performing the fine shifting of the clocks. After initializing the 16-bit Phase DAC at 25%, 50% (mid-scale), and 75%; it was found that the clock distribution PLL locks relatively faster when using mid-scale (2^15). By testing the Phase DAC's linearity, it was confirmed that the circuit resolution is 1.11 ps per code. |
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| .. | ||
| pyusrp_periphs | ||
| usrp_mpm | ||
| aurora_bist_test.py | ||
| CMakeLists.txt | ||
| copy_python_module.cmake | ||
| e320_bist | ||
| lib_helper.cpp | ||
| n3xx_bist | ||
| setup.py.in | ||
| socket_test.py | ||
| test_lmk.py | ||
| tests_periphs.cpp | ||
| tests_periphs.hpp | ||
| usrp_hwd.py | ||
| usrp_update_fs | ||