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Issue: Current code loads FPGA too early while many essential peripherals such as net clocks are not brought up. This change will make sure those are got init before FPGA loaded. Signed-off-by: Trung Tran<trung.tran@ettus.com> |
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| .. | ||
| pyusrp_periphs | ||
| usrp_mpm | ||
| aurora_bist_test.py | ||
| CMakeLists.txt | ||
| copy_python_module.cmake | ||
| e320_bist | ||
| lib_helper.cpp | ||
| n3xx_bist | ||
| setup.py.in | ||
| socket_test.py | ||
| test_lmk.py | ||
| tests_periphs.cpp | ||
| tests_periphs.hpp | ||
| usrp_hwd.py | ||
| usrp_update_fs | ||