The N310 has a feature that allows the front panel GPIOs to be driven by
various sources: The PS, or any of the radio channels. The MPM-based
APIs did not expose any way to change that.
Changes:
- Add MPM APIs to PeripheralManagerBase and n3xx classes
- Improve comments and explanations
- Add host-side hooks into these new APIs in mpmd_mb_controller
- Implement these APIs for N3xx
The N3xx devices will have the option to set the GPIO source to "PS", or
to one of "RF0", "RF1", "RF2", "RF3" (if there are four channels; the
N300 and N320 can only go up to RF1).
Note: The N310 radio does not have separate FP-GPIO banks for channels
0 and 1, which needs to be fixed in a separate commit.
The ad9371 call set_master_clock_rate() can take a while depending on
the rate change, so make it asynchronous in order not to lock out the
reclaimer loop.
- ref_locked failure would throw a warning, even though this can happen
in normal operations, and the return value of the get_ref_locked()
function is all the info needed
- get_fpga_type() doesn't need to be called from e31x_periphs, because
it is not read from the motherboard registers (is read from the
EEPROM)
The clock source on E310 is always internal. This patch removes the
variables regarding the clock source (since they are superfluous). This
fixes a bug where self._clock_source on the e31x class would never get
initialized.
- Remove superfluous INFO logging
- Improve formatting in many places
- Improve Pylint score in various places
- Add tear_down to DB object
- Simplify custom EEPROM code for E310
- Fix time source selection code
- Remove references to GPS_CTRL and GPS_STATUS (are E320 only)
- Move clock source control out of MboardRegs object
Many small cleanups:
- Fix copyright headers
- Fix superfluous imports
- Pull some constants out of classes where appropriate
- Fix formatting
- Improve/fix some docstrings
- Disable specific Pylint warnings where appropriate
- Global catches use BaseException instead of Exception
- Don't use len() for empty checks
- Make sure to declare all self attributes in __init__ (note: this is
particularly of interest for E310, becuase its regular init happens
outside of __init__)
- Compacted some E310 code that had multi-DB checks
This assumes an existence of mboard_regs_control in PeriphManagerBase
and implements most TK controls there. All the *_periphs.py files can
now use a common class for registers, including the TK access, but also
git hash, build date, and device ID access.
This also fixes two issues:
- set_timekeeper_time() and set_tick_period() had a bug that would
incorrectly calculate the upper 32 bits of their respective registers.
- N3xx had a bug that would swap around set time now and next PPS. This
got auto-fixed because the common code never had this bug.
When updating a component like the FPGA, the timeouts for reclaiming get
disabled, because the update can potentially take a long time, during
which the RPC server might not be available.
There was a bug that didn't re-enable the timeouts. The most common case
where this causes issues was when the Ethernet connection was severed
during FPGA reloading, which could lead to UHD losing connection with
MPM altogether (for example because SFPs would come up with a different
IP address). In that case, MPM would remain unreachable until the next
reboot.
Provides a more useful error message if the EEPROM cannot be found at
the specified address. Without this change a generic index out of range
error is raised.
Signed-off-by: michael-west <michael.west@ettus.com>
Some close-in noise was observed on TX when using external references.
This change reduces the noise by changing U19 to select the GPSDO when
references are set to external. Also included is a change to properly
read and apply settings from the configuration file. This allows the
user to further quiet the transmission by adding 'enable_gps=False' to
the configuration file in order to power off the GPSDO.
Signed-off-by: Michael West <michael.west@ettus.com>
When using enable_gps=0, the power to the LTE-Lite GPS chip is turned
off, and neither the reference sources (time/clock) nor the
location/time data (via gpsd) can be used.
This commit disables the gpsdo options for the set_time_source,
set_clock_source, and set_sync_source when enable_gps=0 is used, and
adds logging to inform the user about this.
This behaviour is consistent with X310, where `gpsdo` is only a valid
reference if the GPSDO module is plugged in.
The manual was also updated accordingly.
Openembedded release warrior includes python3-gevent 1.4.0 which
leads to the following error when starting usrp-hwd.py:
ImportError: cannot import name 'BlockingSwitchOutError' from 'gevent.hub'
This commit fixes the issue.
Signed-off-by: Joerg Hofrichter <joerg.hofrichter@ni.com>
This value should be 9 to correspond with the rev J motherboards.
This property was renamed to mboard_last_rev_compat in a previous commit.
But mboard_max_rev is actually a more accurate description,
since it specifies the latest hardware revision that the software
is aware of. I renamed all references back to mboard_max_rev.
This does not change the MPM/UHD API, but it makes the set_freq() call
asynchronous on the MPM side. The upside is that it will release the GIL
if the set_freq() call takes too long, e.g., because of MPM
calibrations.
- Fixes a case where the e320 would be unable to lock to an external 10 MHz
reference
- Previously, calling set_time_source would set the reference clock source to
internal as a side effect
Newer revisions of the E320 and N3xx motherboards use EEPROM version 3,
and store a rev_compat field. The rev_compat is the last revision that
this hardware is compatible with. We now use that instead of simply the
revision.
This includes a rev_compat field, which we can use to identify the last
hardware revision this hardware is compatible with. Example: Say the
current hardware revision is 7, but it is compatible with version 5,
then we store 7 as the current rev, and 5 as the rev_compat. Software
can now check the rev_compat rather than the current rev for
compatibility. This makes MPM more future-proof against minor,
compatible hardware changes.
- Turns the E310 into an MPM device (like N3xx, E320)
- Factor out common code between E320 and E310, maximize sharing between
the two devices
- Remove all pre-MPM E310 code that is no longer needed
- Modify MPM to remove all existing overlays before applying new ones
(this is necessary to enable idle image mode for E310)
Co-authored-by: Virendra Kakade <virendra.kakade@ni.com>
Signed-off-by: Virendra Kakade <virendra.kakade@ni.com>
If the number of channels for embedded mode streaming is 4
(1 for ctrl, 1 for async messages and 2 for data ), we need to
mux the data transport. This is needed for E310
Pull some general functionality out of a specific test case and create
a TestBase class. Future test cases will inherit from TestBase and have
access to this general functionality.
Add unit testing framework to MPM which can be run by calling
"make test". The testing is done using the built in unittest Python
module. Tests can be run on a dev machine or on the USRP itself when
compiling natively.
The N320 has FPGA types (XQ, AQ) which cannot be derived from the mboard
regs in the same way as the non-QSFP variants. We therefore bite the
bullet and hardcode those.
When running
$ n3xx_bist ddr3
The test will now load the AA image if the BIST fails, unless the user
specifies
$ n3xx_bist ddr3 -o skip_load_fpga=1
The rationale is that by default, the AA image is the only one that
includes the DmaFIFO block.
The capability to run the DDR3 BIST is built into the DmaFIFO RFNoC
block, which is not always available. This change performs a quick check
before for its existence before retrieving the throughput values, and
thus can provide a better error message in that case.
We can't guarantee that there is actually a DDR3/DRAM FIFO block on the
image. So, don't run that test by default.
In order to run the DDR3 bist, running `n3xx_bist ddr3` is still valid.
However, it requires an image with the DRAM FIFO enabled.
Without this patch, the N320 code will rely on an error to occur to
determine the non-existence of the N321 LO distribution board. While
this works, it forces an error message where there's no error. This will
first check for the existence of the board before trying to initialize
it.
Issue: Current code loads FPGA too early while many
essential peripherals such as net clocks are not brought up.
This change will make sure those are got init before FPGA loaded.
Signed-off-by: Trung Tran<trung.tran@ettus.com>
Add an argument to the UDP xport_mgr to adjust the xport sorting. This
enables Rhodium to use a different limit from Magnesium. Previously, the
sorting method would overload a link with both of Rhodium's higher-rate
streams.
Fixes Rhodium for changes introduced in b7bab6a. The constructor call
for BfrfsEEPROM didn't match the signature, and Rhodium's EEPROM map
referred to the wrong revision.
Add method to generate GPGGA sensor data in MPM devices. This needs to
be constructed from TPV and SKY sensor data, and matches the GPGGA
sensor functionality in gpsd_iface.cpp.
Previously, the init() procedure of the n3xx class passed either
the user-provided or the default clock_source and time_source values
to initialize the clocking configuration.
When the user did not provide these parameters, the default values
were assigned, overriding whatever configuration the device was
previously initialized with. Therefore, a dboard reinit was forced
when the currently configured state of the N3xx device did not match
the default configuration (i.e. internal sources).
Now, the init() procedure still provides the clock_source and
time_source values; but, if the user does not provide the
parameters, the previously used values are assigned (i.e.
self._clock_source and/or self._time_source).
By the time MPM runs this n3xx init() procedure for the first time,
both self._clock_source and self._time_source have been initialized
with the default internal values anyways in the
_init_ref_clock_and_time() procedure.
This change prevents additional, unnecessary calls to the
set_sync_source() procedure, which ultimately causes a daughterboard
reinitialization when either a new clock or time source is requested.
The update_ref_clock_freq() procedure now updates the self._init_args
value of the Rhodium class daugtherboard objects in MPM to propagate
the latest user-selected arguments for future reference.
gpsd connection is not reliable.
Adding more error handling to re-connect during polling.
Add control flows to get_gps_time in order to give an effect of getting
the value on pps edge.
- This is a combination of 5 commits.
- rh: add lo distribution board gpio expander
- rh: add lo distribution mpm functions
- rh: add code to conditionally initialize lo distribution
- rh: change empty i2c device from exception to assertion
- rh: add lo distribution board control
- Confirmed the Phase DAC to be initialized at mid-scale.
- Confirmed the Phase DAC step resolution for fine clock shifting.
The clock synchronization algorithm relies on the Phase DAC to fine
shift the sampling clocks on each daughterboard.
Only a certain number of DAC codes are required for the actual clock
adjustment, thus a different range of codes may be chosen by
initializing the Phase DAC with a given value. With the selected range,
one may measure the Phase DAC's linearity and step resolution, which
defines how many steps are required when performing the fine shifting
of the clocks.
After initializing the 16-bit Phase DAC at 25%, 50% (mid-scale), and
75%; it was found that the clock distribution PLL locks relatively
faster when using mid-scale (2^15). By testing the Phase DAC's
linearity, it was confirmed that the circuit resolution is 1.11 ps per
code.
- Optimized JESD204B RX/TX links' latency.
- Made JESD latency constant across supported frequencies.
- Checking RX SYSREF capture in the FPGA deframer block.
The JESD204B standard can be linked in such a way to produce a
repeatable, deterministic delay from the framer to deframer. This is
accomplished by setting up a LMFC (local multiframe clock) in both
devices.
The LMFCs are reset whenever a SYSREF edge is captured by the framer
and deframer. Therefore, it is simple to control the LMFC rising edges
in each device by implementing variable delay elements on the SYSREF
pulses to the framer and deframer.
Latency across the JESD204B TX/RX links should remain constant and
deterministic across the supported sampling_clock_rate values. By
testing the roundtrip latency (i.e. FPGA -> TX -> RX -> FPGA) with
different delay values in the FPGA, one may decrease the latency and
provide enough setup and hold margin for the data to be transfered
through each JESD link.
It was found that a different set of SYSREF delay values are required
for sampling_clock_rate = 400 MSPS to match the latency of the other
supported rates.
Add coercing behavior to set_time_source and set_clock_source to
a valid sync source. Also, skip set_sync_source if device already
set to the corresponding one.
