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Author SHA1 Message Date
Francesco Conti
0782b2fee0 Align to QoL changes introduced previously in carfield-cluster 2024-04-16 10:29:02 +00:00
Francesco Conti
ed59950ab7
Merge pull request #45 from pulp-platform/fc/qol-fixes 
Small quality-of-life fixes
 2024-04-16 10:30:11 +02:00
Yvan Tortorella
0bdc1d51b0
Merge pull request #47 from pulp-platform/yt/tout-config 
Add dedicated astral config.
 2024-04-08 17:38:43 +02:00
Riccardo Tedeschi
f208e9f304 Reduce number of cluster cores for Astral 2024-03-29 10:49:25 +01:00
Francesco Conti
e3a8142583 Small quality-of-life fixes 
1) enable compilation without cleaning by overwriting the (anyways broken!)
   modelsim.ini, etc. files on symlink creation
2) work out-of-the-box on non-ETH machines by not defining the QUESTA
   env var
3) make run dependent on $(TARGETS) being built
 2024-03-26 21:14:43 +00:00
Yvan Tortorella
54a233a835 Add dedicated astral config. 2024-03-23 19:36:22 +01:00
Yvan Tortorella
8b508dca78
Merge pull request #44 from pulp-platform/rt/scrubber-api-fix 
Fix offset in scrubber APIs
 2024-02-29 18:18:14 +01:00
Riccardo Tedeschi
5c38feaf15 Fix offset in scrubber APIs 2024-02-29 11:46:41 +01:00
Yvan Tortorella
7c791d0568
Merge pull request #43 from pulp-platform/yt/tcdm-scrubber 
Add APIs for TCDM scrubber.
 2024-02-28 17:09:00 +01:00
Yvan Tortorella
1cbf59cba8 Add APIs for TCDM scrubber. 2024-02-27 19:31:55 +01:00
Yvan Tortorella
e90f6e5327
Merge pull request #41 from pulp-platform/rt/fix-bwruntests 
Fix missing argument `Loader` in `bwruntests.py`
 2024-02-13 09:03:12 +01:00
Riccardo Tedeschi
e09b72160a Fix missing argument Loader in bwruntests.py 2024-02-12 18:40:49 +01:00
Michael Rogenmoser
197d06b6ad Use environment variable for VSIM 2024-02-10 12:28:41 +01:00
Riccardo Tedeschi
b7f2b67774 Update run target in Makefile 
* Pass `APP` variable to the startup TCL script
* Change the executed startup script based on gui or batch simulation
 2024-02-10 12:27:39 +01:00
Yvan Tortorella
cc5186665d Use QUESTA environment variable coupled with vsim. 2024-01-25 15:36:19 +01:00
Riccardo Tedeschi
09b9da49c5 Fix missing space 2024-01-24 00:18:44 +01:00
Yvan Tortorella
90a189ed48 Make DMR regression work on standalone PULP cluster. 2023-10-30 22:15:17 +01:00
Yvan Tortorella
ff4921f39f Added function to write in the cluster internal return value. 2023-10-20 00:10:38 +02:00
Yvan Tortorella
96a6336e8a Referencing to ORIGIN(L2) in .vectors and .l2_data sections. 2023-10-20 00:09:59 +02:00
Yvan Tortorella
45de393f94 Set cluster base address properly. 2023-10-06 16:24:45 +02:00
Yvan Tortorella
89fe257eb9 Added code for HMR. 2023-10-03 22:01:45 +02:00
Yvan Tortorella
8acf75d077 Aligned standard out with Carfield. 2023-10-03 13:09:31 +02:00
Yvan Tortorella
f90f2e6343 Shifting up SDTOUT to allow printf in Carfield configuration (to be 
adjusted with Carfield memory map).
 2023-09-30 08:51:45 +02:00
Yvan Tortorella
464d55d260 Fixed runtime issues and masked the cluster ID if the chip is carfield. 2023-08-11 18:56:27 +02:00
Yvan Tortorella
74d44825ed Fixup: L2 addresses in memory map. 2023-07-12 08:15:03 +02:00
Yvan Tortorella
951a849cce Added carfield-cluster target and remote function to write eoc. 2023-07-11 19:38:37 +02:00
Yvan Tortorella
138d8e3568 Bumped number of cores to 12. 2023-06-26 15:43:16 +02:00
Yvan Tortorella
968f04e35a Making a single cluster with non-zero index successfully work. 2023-06-23 19:02:59 +02:00
Yvan Tortorella
2302536715 Enabled traces for debugging (at least in allocation functions). 2023-06-16 11:09:32 +02:00
Luca Valente
41b428de62 Add target pulp_cluster to test the cluster alone. 2023-04-11 19:25:54 +02:00
Luca Valente
9e9bffbd50 Properly propagate ARCHI_NO_FC to enable boot without the FC. 
Core 0 does the initialization as if it was the FC and then
all the cores enter the main with the proper stack initialization.
 2023-04-11 19:25:48 +02:00
bluew
1ddf10447c Merge branch 'control-pulp' into master 2022-06-17 16:03:01 +02:00
bluew
07c26b52ac pulp-runtime/control-pulp: Use priv_1_12 2022-06-10 18:54:00 +02:00
bluew
7a39de8996 archi: Update privileged level constants 2022-06-10 18:53:40 +02:00
bluew
1059c010a9 treewide: Update JTAG manufacturer code 
PULP Platform now has a code
 2022-06-08 22:14:20 +02:00
aottaviano
1294f4956b pulp-runtime: Add idma APIs 
* Add idma archi and hal sources
* Switch with mchan is still manual
 2022-06-01 13:42:02 +02:00
aottaviano
9724be258c pulp-runtime: Add ARCHI_HAS_DMA_DEMUX property to mchan 
* If the cluster core demux and peripheral demux have a direct connection
to the dma, allow the cluster cores to use this connection.
 2022-06-01 13:41:55 +02:00
aottaviano
77fa6799ed pulp-runtime: Add kairos target 2022-05-17 08:41:20 +02:00
bluew
dd39b06789
Merge pull request #32 from pulp-platform/cv32 
Add PULPissimo/CV32E40P support
 2022-04-08 01:12:31 +02:00
bluew
01df5a78eb Add and update CV32E40P + PULPissimo configurations 2022-04-08 01:10:39 +02:00
bluew
cc161f4134 rules/pulpos/default_rules: Be verbose by default 
Hides too many bugs
 2022-04-08 01:09:59 +02:00
bluew
564ca51f85 pulpissimo_cv32e40p: Use plusargs to pass simulation parameters 2022-04-08 01:00:46 +02:00
bluew
1fd6eeb0d2
Merge pull request #31 from pulp-platform/vsim_version 
vsim compatibility updates
 2022-04-05 18:02:21 +02:00
Michael Rogenmoser
16675bb56b symlink work directory to build folder 2022-03-17 11:16:26 +01:00
Michael Rogenmoser
cbf6592ba2 VSIM variable can override vsim version 2022-03-17 11:15:54 +01:00
Corrado Bonfanti
18ab940220 Add AVS BUS support and basic test 
* Add configuration register to set AVS mode
* Add connections to the SPI controller and txrx interface
* Set idle level of sdio[0] signal of SPI master to '1', according to
the AVS protocol
* Add SPI slave device capability to trigger an event for requesting a read from
master by driving low the MISO (SDATA for AVS) when AVS mode is set.
This happens during tx/rx idle phases
* Add basic Write commit/Read test with pulp-runtime. AVS slave is
simulated in tb_avs.sv and tb_avs_fpga.sv.
 2022-02-10 20:03:42 +01:00
aottaviano
735f29948c treewide: Fix I2C slave module and testsuite 
* Fix wrong signals in RTL hierarchy
* Add I2C slv tb for FPGA wrapper (dump test)
* Add I2C slv tb for ASIC wrapper (irq test)
* Add dump and irq tests

Please enter the commit message for your changes. Lines starting
 2021-12-21 09:45:00 +01:00
bluew
0f4e0e588d pulp-runtime/control-pulp: Fix vector base set and get 
So that rt_irq_set_fc_vector_base() and co. pick the correct
implemention using csr mtvec.
 2021-11-23 11:01:00 +01:00
bluew
82d3ee5f32 pulp-runtime: Link vsim work dir into build dir 2021-11-09 08:49:15 +01:00
bluew
026a98d56a pulp-runtime: Fix uart frequency and bad fll access 
Control-pulp doesn't have an FLL so we hardcode the frequency domain
values. Furthermore we allow these hardcoded values to change depending
on whether we target the FPGA (zcu102) or rtl sim.
 2021-11-04 17:47:57 +01:00