these are just sync'd to the asm.S and checked in.
Eventually, we should migrate that .S file into using
in-line assembly macros, but now that I look at it, I remember
why it hasn't been done yet -- there are some fancy conditionals
used to enable compatibility with different architectures that
I don't know off the top of my head how to translate into
in-line assembly syntax.
The kernel stack offset should be aligned to 16 bytes. Previously it was
aligned to 8 bytes. It's unclear if this was the cause of any issues,
but it is best practice to keep things aligned to 16 bytes.
As part of this, key the atomic instructions off of the CPP macro
presence of atomic instructions.
Signed-off-by: Sean Cross <sean@xobs.io>
Previously, we were creating a fake interrupt that was a "user software
interrupt". Update this to be a "supervisor external interrupt" to fix
hardware resume.
Signed-off-by: Sean Cross <sean@xobs.io>
Atomic operations were previously broken. RISC-V breaks atomic
operations into multiple instructions, and there is some state kept
between those instructions. This state is not visible, and is internal
to the processor.
We were ignoring this state, which resulted in inconsistencies
throughout the system. The following sequence was possible:
1. A thread loads a value, and obtains the `reservation set`
2. A context switch happens on the following instruction
3. A different thread loads the value, modifies it, and continues
4. A third thread (or a different process) loads a value and obtains the
`reservation set`
5. The original thread runs, sees the `reservation set` is held, and
updates the value, clobbering what the second thread did in #3
A workaround for this is to perform a dummy `sc` as part of the context
switch. This invalidates any atomic operations that may be pending.
Signed-off-by: Sean Cross <sean@xobs.io>
This prepares for new calls to init SystemServices and the MemoryManager
so that they can be initialized with something other than a
KernelArguments struct.
Signed-off-by: Sean Cross <sean@xobs.io>
Due to an initial misunderstanding of how the RISC-V is architected,
contexts were going to be an emergent property of the kernel.
However, after further consideration, contexts must now be baked into
the kernel. Switching between contexts can be handled by the scheduler,
but the kernel must keep track of processor registers.
Keep track of context IDs and ensure they are sane. With this patch,
interrupts work, as does basic context switching.
Signed-off-by: Sean Cross <sean@xobs.io>
We were loading both the context and the banked context, which resulted
in an invalid context being selected. This caused a cascading failure.
Load only the lower halfword in order to correctly enter the interrupt
context.
Signed-off-by: Sean Cross <sean@xobs.io>
We now have a concept of context banking. When an interrupt fires, the
process context is banked.
As part of this, process-level data is now stored in the page within the
process itself. This reduces memory consumption and allows us to have
features such as a hash within each process itself.
Signed-off-by: Sean Cross <sean@xobs.io>
