Sean Cross dc097e32d8 kernel: fix atomic operations ... Atomic operations were previously broken. RISC-V breaks atomic operations into multiple instructions, and there is some state kept between those instructions. This state is not visible, and is internal to the processor. We were ignoring this state, which resulted in inconsistencies throughout the system. The following sequence was possible: 1. A thread loads a value, and obtains the `reservation set` 2. A context switch happens on the following instruction 3. A different thread loads the value, modifies it, and continues 4. A third thread (or a different process) loads a value and obtains the `reservation set` 5. The original thread runs, sees the `reservation set` is held, and updates the value, clobbering what the second thread did in #3 A workaround for this is to perform a dummy `sc` as part of the context switch. This invalidates any atomic operations that may be pending. Signed-off-by: Sean Cross <sean@xobs.io>		2023-02-02 23:10:12 +08:00
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riscv32i-unknown-none-elf.a	kernel: fix atomic operations	2023-02-02 23:10:12 +08:00
riscv32imac-unknown-none-elf.a	kernel: fix atomic operations	2023-02-02 23:10:12 +08:00
riscv32imac-unknown-xous-elf.a	kernel: fix atomic operations	2023-02-02 23:10:12 +08:00
riscv32imc-unknown-none-elf.a	kernel: fix atomic operations	2023-02-02 23:10:12 +08:00
riscv64gc-unknown-none-elf.a	kernel: fix atomic operations	2023-02-02 23:10:12 +08:00
riscv64imac-unknown-none-elf.a	kernel: fix atomic operations	2023-02-02 23:10:12 +08:00