saymrwulf/xous-core
1
0
Fork 0
mirror of https://github.com/saymrwulf/xous-core.git synced 2026-11-04 04:27:34 +00:00
Code Issues Projects Releases Packages Wiki Activity Actions
xous-core/kernel
History
Sean Cross dc097e32d8 kernel: fix atomic operations 
Atomic operations were previously broken. RISC-V breaks atomic
operations into multiple instructions, and there is some state kept
between those instructions. This state is not visible, and is internal
to the processor.

We were ignoring this state, which resulted in inconsistencies
throughout the system. The following sequence was possible:

1. A thread loads a value, and obtains the `reservation set`
2. A context switch happens on the following instruction
3. A different thread loads the value, modifies it, and continues
4. A third thread (or a different process) loads a value and obtains the
   `reservation set`
5. The original thread runs, sees the `reservation set` is held, and
   updates the value, clobbering what the second thread did in #3

A workaround for this is to perform a dummy `sc` as part of the context
switch. This invalidates any atomic operations that may be pending.

Signed-off-by: Sean Cross <sean@xobs.io>
2023-02-02 23:10:12 +08:00
..
bin kernel: fix atomic operations 2023-02-02 23:10:12 +08:00
src kernel: fix atomic operations 2023-02-02 23:10:12 +08:00
assemble.ps1 kernel: compatibility with riscv32imac-unknown-xous-elf 2021-08-18 18:14:24 +08:00
assemble.sh Switch to using env to find the path to bash. 2022-03-28 16:43:47 -06:00
build.rs xous: Use CARGO_CFG_TARGET_OS in build scripts. 2022-10-12 19:03:46 +02:00
Cargo.toml bump kernel package version 2023-02-01 22:45:37 +08:00
link.x add an "endcap" to the kernel region 2023-01-17 23:07:05 +08:00
README.md adding license info to README 2021-01-25 14:57:39 +01:00

README.md

Xous Kernel

This contains the core kernel for Xous. It requires a stage 1 loader in order to start up, as it assumes the system is already running in Supervisor mode.

Building

To build the kernel, you will need a riscv32 target for Rust. Possible targets include riscv32i-unknown-none-elf, riscv32imac-unknown-none-elf, or riscv32imac-unknown-xous-elf.

  1. Decide what target you want. For simple, embedded systems this could be riscv32i-unknown-none-elf, and for more complex systems with compressed instructions you could use riscv32imac-unknown-none-elf.
  2. Get Rust. Go to https://rustup.rs/ and follow its instructions.
  3. Install the proper toolchain: rustup target add ${target_arch}
  4. Build the kernel: cargo build --release --target ${target_arch}

Using

To use the kernel, you must package it up into an arguments binary with xous-tools.

Testing

TBD

Contribution Guidelines

Contributor Covenant

Please see CONTRIBUTING for details on how to make a contribution.

Please note that this project is released with a Contributor Code of Conduct. By participating in this project you agree to abide its terms.

License

Copyright © 2020

This project is licensed under the Apache License 2.0 LICENSE. For accurate information, please check individual files.