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Due to an initial misunderstanding of how the RISC-V is architected, contexts were going to be an emergent property of the kernel. However, after further consideration, contexts must now be baked into the kernel. Switching between contexts can be handled by the scheduler, but the kernel must keep track of processor registers. Keep track of context IDs and ensure they are sane. With this patch, interrupts work, as does basic context switching. Signed-off-by: Sean Cross <sean@xobs.io> |
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| riscv32i-unknown-none-elf.a | ||
| riscv32imac-unknown-none-elf.a | ||
| riscv32imc-unknown-none-elf.a | ||
| riscv64gc-unknown-none-elf.a | ||
| riscv64imac-unknown-none-elf.a | ||