primarily modify the loading method to mark pages with A/D flags
as needed to work around lack of A/D handling in the trap handler
of Xous.
Also inside main.rs is a todo list for polishing off the vex-ii
port and turning into something actually sustainable for Denarius
once we have more of a full SoC model available.
Spinor is the one location where memory changes out "from underneath
the CPU" in a cacheable region. This happens when we update a block
of FLASH.
Vex-ii has a physically tagged d-cache, but the cbo.flush instruction
needs the *virtual* address to be passed (it then goes through a page
walk or TLB lookup to resolve the tag). The virtual address only
exists and can be correctly resolved to a physical address in the
process space of the owner of the region that maps to the SPINOR
FLASH. Thus, we introduce a flush routine in the lib.rs side that
calls the cbo.flush instruction on every line that has been potentially
modified by the flash write routine.
Note that cbo.flush is not yet natively supported by Rust stable,
so it's coded as a series of hex words fixed to a given register (a0)
to avoid introducing a nightly dependency. Once the cbo.flush
assembly instructions stabilize we can make the assembly read more
nicely, but functionally it should compile to exactly the same code.
we don't have a curve25519 accelerator on the vexii-test device
due to a lack of space to fit it. so for vexii-test targets
we swap in the u32 (vs u32e) backend.
This requires re-writing the config.toml file based on the
presence (or absence) of a vexii-test flag.
The "main" product line is affected here in that the UART
init is hosted above the trng init. This should have no impact
on security or boot time, but allows us to more easily debug
TRNG init issues. This is necessary because in the vexii test
version the XADC interface is broken by the slower clocking
and I'm not taking the time to trace down that issue as it
does nothing to further the goal of testing the vex-ii core
in a non-production config.
legacy_int handler allows vex-ii to emulate/behave like the vex-i
in terms of interrupt handling.
eventually this will be replaced with/augmeted by a PLIC.
1. Instead of panicing when a page is re-requested, return an
error message to the caller. This allows us to have the UART
pre-allocated by the loader and the kernel to request it prophylactically
2. add A/D flags for R/W pages in vexii-testing. This is a work-around
until we have proper A/D tracking in the page lifecycle mechanism.
This will also be the version we'll use for the daric chip once
it's available; the prior software-only version hack for MPW will
be retired soon.
Note that only AES-256 is implemented in this commit, AES-128
isn't used on the system and so is provided as a software-only
fallback path.
This will help keep the command somewhat organized as things
are developed.
Also provides some templating for e.g. how to handle carriage
returns, etc.
this is a minimal target for building test images that need
none of the xous goodies, but may rely upon e.g. APIs and
libraries. Closer to coding for a baremetal embedded system.
