NACK bit is now checked after running the transaction, and if
it is set an appropriate error code is returned.
The trait implementation for i2c baremetal calls is also
updated in this commit
in the Xous context, because the IRQ banks are owned by a global
object, not every server can simply refer to the IRQ bits by just
dereferencing a pointer. Instead, it needs to send a message to
the cram_hal_service with an API number which then catches this
and does the dereference on behalf of the caller.
multiple IRQs related to the UDMA will eventually get mapped into
the global IRQ handler for UDMA. Create an enum type that will
help us differentiate this and add a trait that returns the raw bits
for a given IRQ type.
Probably a fancier wrapper should be made to interptet the IRQ
bits but unfortunately there isn't a uniform pattern to the IRQ
mappings, it's pretty much whatever fit into the IRQ space based
on the underlying function. At the moment not even sure if this
is the right register to be chasing, so we'll use this for probing
that aspect and then get fancy later, maybe.
the switch based on target is now absorbed into the new() function.
This paves the way for us to add more CSR ranges into the global
configuration object, i.e. IRQ csrs for I2C.
our implementantation of Buffer can't (currently) dynamically grow
the size of the object to serialize things that are bigger than
a page, so we have to enforce Vec-like objects to have a serialized
size of less than the page limit.
This is a bit of a moving target because it depends on implementation
specific details. A conservative bodge was put in to try and
work around this problem for now.
This was introducing a mysterious "line" artifact on text rendering
in new systems.
Probably need to do some real on-device testing of this change
because the automated tests won't catch a dirty bit error on
the LCD.
cramium-soc i think should be deprecated everywhere because
it is redundant with the board targets: anywhere you see a board
target that includes the crossbar soc it should also transitively
pull in the cramium-soc dependency equivalents.
we'll chase this out more later, but for now we're just trying
to get the PDDB to compile
This is a bad idea because yield_slice() causes the active
process to hand off to a new one (without an IRQ). However,
the idea of most flash operations is we really want them
atomic - we can't have something else decide to go and muck
with flash while say, we are waiting for a page erase to
complete. So, implement spin locking to block the CPU
during phases where the hardware operation is non-interruptable.
BOOKEND test sentinels are moved out of xous-rs, and into the
board definitions allowing us more flexibility on configuration
board-specific test configs (before it was a xous-wide constant,
which seems a bad idea because it makes migrating test infra
hard as the manufacturing infra updates)
MMAP_VIRT as a range is also added is this commit
this allows us move board-specific parameters out of xous-rs
and into a board library that is consistent with the new board
libraries, reducing special case code for Precursor
