mirror of
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- Based on feedback from ADI, updated SYSREF sequencing for
meeting deterministic latency requirements.
- Changed majority of register addresses in nijesdcore.py to
constants.
- Corrected write data to SYSREF_CAPTURE_CONTROL to produce
the correct SYSREF toggle rate inside the FPGA.
Signed-off-by: djepson1 <daniel.jepson@ni.com>
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|---|---|---|
| .. | ||
| usrp_mpm | ||
| aurora_bist_test.py | ||
| CMakeLists.txt | ||
| converters.hpp | ||
| copy_python_module.cmake | ||
| lib_helper.cpp | ||
| n3xx_bist | ||
| pyusrp_periphs.cpp | ||
| setup.py.in | ||
| socket_test.py | ||
| test_lmk.py | ||
| tests_periphs.cpp | ||
| tests_periphs.hpp | ||
| usrp_hwd.py | ||