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- Based on feedback from ADI, updated SYSREF sequencing for
meeting deterministic latency requirements.
- Changed majority of register addresses in nijesdcore.py to
constants.
- Corrected write data to SYSREF_CAPTURE_CONTROL to produce
the correct SYSREF toggle rate inside the FPGA.
Signed-off-by: djepson1 <daniel.jepson@ni.com>
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| mpm_test_main.cpp | ||