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https://github.com/saymrwulf/uhd.git
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mg: Updated JESD204b init seq and documentation.
- Based on feedback from ADI, updated SYSREF sequencing for
meeting deterministic latency requirements.
- Changed majority of register addresses in nijesdcore.py to
constants.
- Corrected write data to SYSREF_CAPTURE_CONTROL to produce
the correct SYSREF toggle rate inside the FPGA.
Signed-off-by: djepson1 <daniel.jepson@ni.com>
This commit is contained in:
djepson1
Martin Braun
parent
6858b05357
commit
4e0600b00a
2 changed files with 65 additions and 41 deletions
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@ -273,64 +273,76 @@ class Magnesium(DboardManagerBase):
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def init_jesd(self, uio):
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"""
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Bring up the JESD link between Mykonos and the N310
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Bring up the JESD link between Mykonos and the N310.
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"""
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self.log.trace("Creating jesdcore object")
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self.jesdcore = nijesdcore.NIMgJESDCore(uio)
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# CPLD Register Definition
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MYKONOS_CONTROL = 0x13
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self.log.trace("Checking JESD core...")
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self.log.trace("Creating jesdcore object")
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self.jesdcore = nijesdcore.NIMgJESDCore(uio, self.slot_idx)
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self.jesdcore.check_core()
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self.log.trace("Initializing LMK...")
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self.jesdcore.unreset_qpll()
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self.jesdcore.init()
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self.log.trace("Resetting Mykonos...")
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# YIKES!!! Where does this go?!? CPLD?
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# self.jesdcore.reset_mykonos() #not sure who owns the reset
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self.cpld_poke16(0x13, 0x1)
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self.cpld_poke16(0x13, 0x0)
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self.log.trace("Pulsing Mykonos Hard Reset...")
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self.cpld_regs.poke16(MYKONOS_CONTROL, 0x1)
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time.sleep(0.001) # No spec here, but give it some time to reset.
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self.cpld_regs.poke16(MYKONOS_CONTROL, 0x0)
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time.sleep(0.001) # No spec here, but give it some time to enable.
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self.log.trace("Initializing Mykonos...")
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self.mykonos.begin_initialization()
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# Multi-chip Sync requires two SYSREF pulses at least 17us apart.
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self.jesdcore.send_sysref_pulse()
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time.sleep(0.001)
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self.jesdcore.send_sysref_pulse()
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self.mykonos.finish_initialization()
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self.log.trace("Starting Mykonos framer...")
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self.mykonos.start_jesd_tx()
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self.jesdcore.send_sysref_pulse()
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self.log.trace("Resetting FPGA deframer...")
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self.jesdcore.init_deframer()
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self.log.trace("Resetting FPGA framer...")
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self.log.trace("Starting JESD204b Link Initialization...")
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# Generally, enable the source before the sink. Start with the DAC side.
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self.log.trace("Starting FPGA framer...")
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self.jesdcore.init_framer()
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self.log.trace("Starting Mykonos deframer...")
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self.mykonos.start_jesd_rx()
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self.log.trace("Enable LMFC and send")
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# Now for the ADC link. Note that the Mykonos framer will not start issuing CGS
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# characters until SYSREF is received by the framer. Therefore we enable the
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# framer in Mykonos and the FPGA, send a SYSREF pulse to everyone, and then
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# start the deframer in the FPGA.
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self.log.trace("Starting Mykonos framer...")
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self.mykonos.start_jesd_tx()
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self.log.trace("Enable FPGA SYSREF Receiver.")
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self.jesdcore.enable_lmfc()
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self.jesdcore.send_sysref_pulse()
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time.sleep(0.2)
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self.log.trace("Starting FPGA deframer...")
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self.jesdcore.init_deframer()
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# Allow a bit of time for CGS/ILA to complete.
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time.sleep(0.100)
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if not self.jesdcore.get_framer_status():
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self.log.error("FPGA Framer Error!")
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raise Exception('JESD Core Framer is not synced!')
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if ((self.mykonos.get_deframer_status() & 0x7F) != 0x28):
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self.log.error("Mykonos Deframer Error: 0x{:X}".format((self.mykonos.get_deframer_status() & 0x7F)))
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raise Exception('Mykonos Deframer is not synced!')
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if not self.jesdcore.get_deframer_status():
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self.log.error("FPGA Deframer Error!")
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raise Exception('JESD Core Deframer is not synced!')
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if (self.mykonos.get_framer_status() & 0xFF) != 0x3E:
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if ((self.mykonos.get_framer_status() & 0xFF) != 0x3E):
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self.log.error("Mykonos Framer Error: 0x{:X}".format((self.mykonos.get_framer_status() & 0xFF)))
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raise Exception('Mykonos Framer is not synced!')
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if (self.mykonos.get_multichip_sync_status() & 0xB) != 0xB:
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if ((self.mykonos.get_multichip_sync_status() & 0xB) != 0xB):
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raise Exception('Mykonos multi chip sync failed!')
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self.log.info("JESD204B Link Initialization & Training Complete")
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self.log.trace("JESD fully synced and ready")
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def dump_jesd_core(self):
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radio_regs = UIO(label="dboard-regs-{}".format(self.slot_idx))
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for i in range(0x2000, 0x2110, 0x10):
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print(("0x%04X " % i), end=' ')
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for j in range(0, 0x10, 0x4):
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print(("%08X" % self.radio_regs.peek32(i + j)), end=' ')
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print(("%08X" % radio_regs.peek32(i + j)), end=' ')
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print("")
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@ -31,6 +31,17 @@ class NIMgJESDCore(object):
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Arguments:
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regs -- regs class to use for peek/poke
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"""
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MGT_RECEIVER_CONTROL = 0x2040
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MGT_RX_DESCRAMBLER_CONTROL = 0x2050
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MGT_TRANSMITTER_CONTROL = 0x2060
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MGT_TX_TRANSCEIVER_CONTROL = 0x2064
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MGT_TX_SCRAMBLER_CONTROL = 0x2068
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SYSREF_CAPTURE_CONTROL = 0x2078
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JESD_SIGNATURE_REG = 0x2100
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JESD_REVISION_REG = 0x2104
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def __init__(self, regs, slot_idx=0):
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self.regs = regs
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self.log = get_logger("NIMgJESDCore-{}".format(slot_idx))
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@ -47,11 +58,11 @@ class NIMgJESDCore(object):
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Verify JESD core returns correct ID
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"""
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self.log.trace("Checking JESD Core...")
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if self.regs.peek32(0x2100) != 0x4A455344:
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if self.regs.peek32(self.JESD_SIGNATURE_REG) != 0x4A455344:
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raise Exception('JESD Core signature mismatch! Check that core is mapped correctly')
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#if self.regs.peek32(0x2104) != 0xFF
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#if self.regs.peek32(JESD_REVISION_REG) != 0xFF
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#error here for date revision mismatch
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self.log.trace("JESD Core build code: {0}".format(hex(self.regs.peek32(0x2104))))
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self.log.trace("JESD Core build code: {0}".format(hex(self.regs.peek32(self.JESD_REVISION_REG))))
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self.log.trace("DB Slot #: {}".format( (self.regs.peek32(0x630) & 0x10000) >> 16 ))
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self.log.trace("DB PID: {:X}".format( self.regs.peek32(0x630) & 0xFFFF ))
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return True
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@ -59,34 +70,34 @@ class NIMgJESDCore(object):
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def init_deframer(self):
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" Initialize deframer "
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self.log.trace("Initializing deframer...")
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self.regs.poke32(0x2040, 0x2)
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self.regs.poke32(0x2050, 0x0)
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self.regs.poke32(self.MGT_RECEIVER_CONTROL, 0x2)
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self.regs.poke32(self.MGT_RX_DESCRAMBLER_CONTROL, 0x0)
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self._gt_reset('rx', reset_only=False)
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self.regs.poke32(0x2040, 0x0)
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self.regs.poke32(self.MGT_RECEIVER_CONTROL, 0x0)
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def init_framer(self):
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" Initialize framer "
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self.log.trace("Initializing framer...")
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# Disable DAC Sync from requesting CGS & Stop Deframer
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self.regs.poke32(0x2060, 0x2002)
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self.regs.poke32(self.MGT_TRANSMITTER_CONTROL, 0x2002)
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# Reset, unreset, and check the GTs
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self._gt_reset('tx', reset_only=False)
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# MGT phy control... enable TX Driver Swing
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self.regs.poke32(0x2064, 0xF0000)
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self.regs.poke32(self.MGT_TX_TRANSCEIVER_CONTROL, 0xF0000)
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time.sleep(0.001)
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# Bypass scrambler and disable char replacement
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self.regs.poke32(0x2068, 0x1)
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self.regs.poke32(self.MGT_TX_SCRAMBLER_CONTROL, 0x1)
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# Check for Framer in Idle state
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rb = self.regs.peek32(0x2060)
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rb = self.regs.peek32(self.MGT_TRANSMITTER_CONTROL)
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if rb & 0x100 != 0x100:
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raise Exception('TX Framer is not idle after reset')
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# Enable the framer and incoming DAC Sync
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self.regs.poke32(0x2060, 0x1000)
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self.regs.poke32(0x2060, 0x0001)
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self.regs.poke32(self.MGT_TRANSMITTER_CONTROL, 0x1000)
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self.regs.poke32(self.MGT_TRANSMITTER_CONTROL, 0x0001)
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def get_framer_status(self):
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" Return True if framer is in good status "
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rb = self.regs.peek32(0x2060)
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rb = self.regs.peek32(self.MGT_TRANSMITTER_CONTROL)
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self.log.trace("FPGA Framer status: {0}".format(hex(rb & 0xFF0)))
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if rb & (0b1 << 8) == 0b1 << 8:
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self.log.warning("Framer warning: Framer is Idle!")
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@ -98,7 +109,7 @@ class NIMgJESDCore(object):
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def get_deframer_status(self):
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" Return True if deframer is in good status "
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rb = self.regs.peek32(0x2040)
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rb = self.regs.peek32(self.MGT_RECEIVER_CONTROL)
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self.log.trace("FPGA Deframer status: {0}".format(hex(rb & 0xFFFFFFFF)))
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if rb & (0b1 << 2) == 0b0 << 2:
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self.log.warning("Deframer warning: Code Group Sync failed to complete!")
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@ -117,13 +128,14 @@ class NIMgJESDCore(object):
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self._gt_reset('tx', reset_only=True)
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self._gt_reset('rx', reset_only=True)
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self._gt_pll_lock_control()
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self.regs.poke32(0x2078, 0x40)
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# Disable SYSREF Sampler
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self.regs.poke32(self.SYSREF_CAPTURE_CONTROL, 0x9800040)
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def enable_lmfc(self):
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"""
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Enable LMFC generator in FPGA. This step is woefully incomplete, but this call will work for now.
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"""
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self.regs.poke32(0x2078, 0)
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self.regs.poke32(self.SYSREF_CAPTURE_CONTROL, 0x9800000)
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def send_sysref_pulse(self):
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"""
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