- Replace mykonos finish_initialization with async version
- Replace myknonos setup_cal with async version
- Remove disable_timeout on rpc_server init()
The log output at level 'INFO' was pretty cluttered. This cleans up the
log messages at the higher levels. In some cases, log message typos or
capitalizations were also fixed.
Add axi_bitq support. In order for this to work we need several
conditions to be true:
- Updated openocd
- FPGA image with axi_bitq built in and hooked up to correct pins
- Updated overlays matching the FPGA image
- An svf file with correct max frequency <= 10MHz
Signed-off-by: Moritz Fischer <moritz.fischer@ettus.com>
Using string expression instead of passing in a total hex value.
Now user can passed in for example: init_cals=DEFAULT or
init_cals=BASIC|TX_QEC_INIT
Reviewed-by: Martin Braun <martin.braun@ettus.com>
Slot A and Slot B are different in how the JESD lanes are connected.
We now pass in different deserializer_lane_xbar config values for each slot.
Reviewed-by: Martin Braun <martin.braun@ettus.com>
Reviewed-by: Daniel Jepson <daniel.jepson@ettus.com>
Reviewed-by: Mark Meserve <mark.meserve@ni.com>
There was a theoretical chance otherwise that we forgot to set the
ref_clock_freq value and it set up the LMK incorrectly.
Reviewed-by: Daniel Jepson <daniel.jepson@ettus.com>
Now checks the oldest-compat-rev register. Current rev is read out for
logging purposes.
Reviewed-by: Daniel Jepson <daniel.jepson@ettus.com>
Reviewed-by: Moritz Fischer <moritz.fischer@ettus.com>
Refactoring to use the C++-based UIO objects. The Liberio and Ethernet
objects now open the UIO before using it, and close it once done.
Reviewed-By: Martin Braun <martin.braun@ettus.com>
- Moved nijesdcore to cores/
- Moved udev, net, dtoverlay, uio to sys_utils/
- Made all imports non-relative (except in __init__.py files)
- Removed some unnecessary imports
- Reordered some imports for Python conventions
- re-structured Magnesium.init_jesd() sequence to accomodate the reconfiguration
- added DRP access protocols to nijesdcore.py
- cleaned up a few comments and log statements in nijesdcore.py for flow
Reviewed-By: Martin Braun <martin.braun@ettus.com>
- ClockSynchronizer object has no more permanent lifetime
- DboardClockControl object lives within `with' statement
- dboard_ctrl_regs are limited to init()
Previously, the daughterboard requested an overlay file based on SFP
preference using magic values. This commit moves the decision making to
the peripheral manager, which uses our singular name (ie 'n3xx' for the
N310).
The clock_synchronizer, jesdcore, and dboard_clk_control objects don't
need to exist for the full lifetime of the Magnesium class. Having them
around complicates management of UIO file descriptors.
- re-wrote portions of the LMK driver for flexible rates and configuration
- tweaked TDC driver for compatibility and ease of debugging
- updated comments and log statements throughout for uniformity
