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Add axi_bitq support. In order for this to work we need several conditions to be true: - Updated openocd - FPGA image with axi_bitq built in and hooked up to correct pins - Updated overlays matching the FPGA image - An svf file with correct max frequency <= 10MHz Signed-off-by: Moritz Fischer <moritz.fischer@ettus.com> |
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| .. | ||
| __init__.py | ||
| base.py | ||
| CMakeLists.txt | ||
| eiscat.py | ||
| lmk_eiscat.py | ||
| lmk_mg.py | ||
| magnesium.py | ||
| magnesium_update_cpld.py | ||
| test.py | ||
| unknown.py | ||