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Add axi_bitq support. In order for this to work we need several conditions to be true: - Updated openocd - FPGA image with axi_bitq built in and hooked up to correct pins - Updated overlays matching the FPGA image - An svf file with correct max frequency <= 10MHz Signed-off-by: Moritz Fischer <moritz.fischer@ettus.com> |
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| .. | ||
| usrp_mpm | ||
| aurora_bist_test.py | ||
| CMakeLists.txt | ||
| converters.hpp | ||
| copy_python_module.cmake | ||
| lib_helper.cpp | ||
| n3xx_bist | ||
| pyusrp_periphs.cpp | ||
| setup.py.in | ||
| socket_test.py | ||
| test_lmk.py | ||
| tests_periphs.cpp | ||
| tests_periphs.hpp | ||
| usrp_hwd.py | ||