When running
$ n3xx_bist ddr3
The test will now load the AA image if the BIST fails, unless the user
specifies
$ n3xx_bist ddr3 -o skip_load_fpga=1
The rationale is that by default, the AA image is the only one that
includes the DmaFIFO block.
The capability to run the DDR3 BIST is built into the DmaFIFO RFNoC
block, which is not always available. This change performs a quick check
before for its existence before retrieving the throughput values, and
thus can provide a better error message in that case.
We can't guarantee that there is actually a DDR3/DRAM FIFO block on the
image. So, don't run that test by default.
In order to run the DDR3 bist, running `n3xx_bist ddr3` is still valid.
However, it requires an image with the DRAM FIFO enabled.
Without this patch, the N320 code will rely on an error to occur to
determine the non-existence of the N321 LO distribution board. While
this works, it forces an error message where there's no error. This will
first check for the existence of the board before trying to initialize
it.
Issue: Current code loads FPGA too early while many
essential peripherals such as net clocks are not brought up.
This change will make sure those are got init before FPGA loaded.
Signed-off-by: Trung Tran<trung.tran@ettus.com>
Add an argument to the UDP xport_mgr to adjust the xport sorting. This
enables Rhodium to use a different limit from Magnesium. Previously, the
sorting method would overload a link with both of Rhodium's higher-rate
streams.
Fixes Rhodium for changes introduced in b7bab6a. The constructor call
for BfrfsEEPROM didn't match the signature, and Rhodium's EEPROM map
referred to the wrong revision.
Add method to generate GPGGA sensor data in MPM devices. This needs to
be constructed from TPV and SKY sensor data, and matches the GPGGA
sensor functionality in gpsd_iface.cpp.
Previously, the init() procedure of the n3xx class passed either
the user-provided or the default clock_source and time_source values
to initialize the clocking configuration.
When the user did not provide these parameters, the default values
were assigned, overriding whatever configuration the device was
previously initialized with. Therefore, a dboard reinit was forced
when the currently configured state of the N3xx device did not match
the default configuration (i.e. internal sources).
Now, the init() procedure still provides the clock_source and
time_source values; but, if the user does not provide the
parameters, the previously used values are assigned (i.e.
self._clock_source and/or self._time_source).
By the time MPM runs this n3xx init() procedure for the first time,
both self._clock_source and self._time_source have been initialized
with the default internal values anyways in the
_init_ref_clock_and_time() procedure.
This change prevents additional, unnecessary calls to the
set_sync_source() procedure, which ultimately causes a daughterboard
reinitialization when either a new clock or time source is requested.
The update_ref_clock_freq() procedure now updates the self._init_args
value of the Rhodium class daugtherboard objects in MPM to propagate
the latest user-selected arguments for future reference.
gpsd connection is not reliable.
Adding more error handling to re-connect during polling.
Add control flows to get_gps_time in order to give an effect of getting
the value on pps edge.
- This is a combination of 5 commits.
- rh: add lo distribution board gpio expander
- rh: add lo distribution mpm functions
- rh: add code to conditionally initialize lo distribution
- rh: change empty i2c device from exception to assertion
- rh: add lo distribution board control
- Confirmed the Phase DAC to be initialized at mid-scale.
- Confirmed the Phase DAC step resolution for fine clock shifting.
The clock synchronization algorithm relies on the Phase DAC to fine
shift the sampling clocks on each daughterboard.
Only a certain number of DAC codes are required for the actual clock
adjustment, thus a different range of codes may be chosen by
initializing the Phase DAC with a given value. With the selected range,
one may measure the Phase DAC's linearity and step resolution, which
defines how many steps are required when performing the fine shifting
of the clocks.
After initializing the 16-bit Phase DAC at 25%, 50% (mid-scale), and
75%; it was found that the clock distribution PLL locks relatively
faster when using mid-scale (2^15). By testing the Phase DAC's
linearity, it was confirmed that the circuit resolution is 1.11 ps per
code.
- Optimized JESD204B RX/TX links' latency.
- Made JESD latency constant across supported frequencies.
- Checking RX SYSREF capture in the FPGA deframer block.
The JESD204B standard can be linked in such a way to produce a
repeatable, deterministic delay from the framer to deframer. This is
accomplished by setting up a LMFC (local multiframe clock) in both
devices.
The LMFCs are reset whenever a SYSREF edge is captured by the framer
and deframer. Therefore, it is simple to control the LMFC rising edges
in each device by implementing variable delay elements on the SYSREF
pulses to the framer and deframer.
Latency across the JESD204B TX/RX links should remain constant and
deterministic across the supported sampling_clock_rate values. By
testing the roundtrip latency (i.e. FPGA -> TX -> RX -> FPGA) with
different delay values in the FPGA, one may decrease the latency and
provide enough setup and hold margin for the data to be transfered
through each JESD link.
It was found that a different set of SYSREF delay values are required
for sampling_clock_rate = 400 MSPS to match the latency of the other
supported rates.
Add coercing behavior to set_time_source and set_clock_source to
a valid sync source. Also, skip set_sync_source if device already
set to the corresponding one.
