Michael Rogenmoser 2ba1be662d Update Macro naming		2021-02-02 11:09:28 +01:00
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archi	Update Macro naming	2021-02-02 11:09:28 +01:00
bench	fix ri5cy compatibility	2021-01-22 21:11:35 +01:00
chips	FIxed wrong size of pos_freq_domains	2020-03-05 15:56:56 +01:00
data	Fixed issue with data placement leading to corruption	2020-01-14 23:02:03 +01:00
hal	fix ri5cy compatibility	2021-01-22 21:11:35 +01:00
implem	change spr_read and write from __builtin to hal for irq	2020-12-07 09:40:15 +01:00
pulp.h	Cluster stacks are now dynamically allocated to avoid long preloading on netlist sim	2020-04-02 11:09:49 +02:00