saymrwulf/pulp-runtime
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5 commits

Author SHA1 Message Date
bluew
026a98d56a pulp-runtime: Fix uart frequency and bad fll access 
Control-pulp doesn't have an FLL so we hardcode the frequency domain
values. Furthermore we allow these hardcoded values to change depending
on whether we target the FPGA (zcu102) or rtl sim.
 2021-11-04 17:47:57 +01:00
Manuel Eggimann
dc012f0c54 Add config for nexys FPGA board 2021-06-24 22:02:19 +02:00
Manuel Eggimann
763fa6f72b Add SOC_FREQUENCY to fpga specific runtime configuration 2021-06-24 22:01:49 +02:00
Manuel Eggimann
5b2fdb62a2 Add additional FPGA config files 2020-03-05 16:16:31 +01:00
Germain Haugou
31052776f8 Added runner 2019-12-17 22:14:17 +01:00