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emulation: ec: add new riscv suffixes for csr/fence

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The riscv foundation changed the descriptor of riscv cores. We must now
add "_zicsr_zifencei" to the "rv32i" designation in order to ensure we
have access to CSRs and the "FENCE.I" instruction.

Signed-off-by: Sean Cross <sean@xobs.io>
This commit is contained in:
Sean Cross 2023-12-29 18:36:31 +08:00
parent 5260ef9f5a
commit 08abed53bd
1 changed files with 1 additions and 1 deletions
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2
emulation/ec/betrusted-ec.repl
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@ -1,5 +1,5 @@
cpu: CPU.VexRiscv @ sysbus
cpuType: "rv32i"
cpuType: "rv32i_zicsr_zifencei"
PerformanceInMips: 6
uart: UART.LiteX_UART @ {