From 08abed53bdcf6118c754467a68eb7ba70960eecc Mon Sep 17 00:00:00 2001 From: Sean Cross Date: Fri, 29 Dec 2023 18:36:31 +0800 Subject: [PATCH] emulation: ec: add new riscv suffixes for csr/fence The riscv foundation changed the descriptor of riscv cores. We must now add "_zicsr_zifencei" to the "rv32i" designation in order to ensure we have access to CSRs and the "FENCE.I" instruction. Signed-off-by: Sean Cross --- emulation/ec/betrusted-ec.repl | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/emulation/ec/betrusted-ec.repl b/emulation/ec/betrusted-ec.repl index e1918ef07..5ac00d7ec 100644 --- a/emulation/ec/betrusted-ec.repl +++ b/emulation/ec/betrusted-ec.repl @@ -1,5 +1,5 @@ cpu: CPU.VexRiscv @ sysbus - cpuType: "rv32i" + cpuType: "rv32i_zicsr_zifencei" PerformanceInMips: 6 uart: UART.LiteX_UART @ {