mirror of
https://github.com/saymrwulf/uhd.git
synced 2026-05-16 21:10:10 +00:00
4e0600b00a
- Based on feedback from ADI, updated SYSREF sequencing for
meeting deterministic latency requirements.
- Changed majority of register addresses in nijesdcore.py to
constants.
- Corrected write data to SYSREF_CAPTURE_CONTROL to produce
the correct SYSREF toggle rate inside the FPGA.
Signed-off-by: djepson1 <daniel.jepson@ni.com>
192 lines
7.7 KiB
Python
192 lines
7.7 KiB
Python
#
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# Copyright 2017 Ettus Research (National Instruments)
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#
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# This program is free software: you can redistribute it and/or modify
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# it under the terms of the GNU General Public License as published by
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# the Free Software Foundation, either version 3 of the License, or
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# (at your option) any later version.
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#
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# This program is distributed in the hope that it will be useful,
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# but WITHOUT ANY WARRANTY; without even the implied warranty of
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# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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# GNU General Public License for more details.
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#
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# You should have received a copy of the GNU General Public License
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# along with this program. If not, see <http://www.gnu.org/licenses/>.
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#
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"""
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JESD FPGA Core Interface
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"""
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import time
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from builtins import hex
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from builtins import object
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from .mpmlog import get_logger
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class NIMgJESDCore(object):
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"""
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Provide interface for the FPGA JESD Core.
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Works with Magnesium/Mykonos daughterboards only.
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Arguments:
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regs -- regs class to use for peek/poke
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"""
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MGT_RECEIVER_CONTROL = 0x2040
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MGT_RX_DESCRAMBLER_CONTROL = 0x2050
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MGT_TRANSMITTER_CONTROL = 0x2060
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MGT_TX_TRANSCEIVER_CONTROL = 0x2064
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MGT_TX_SCRAMBLER_CONTROL = 0x2068
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SYSREF_CAPTURE_CONTROL = 0x2078
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JESD_SIGNATURE_REG = 0x2100
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JESD_REVISION_REG = 0x2104
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def __init__(self, regs, slot_idx=0):
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self.regs = regs
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self.log = get_logger("NIMgJESDCore-{}".format(slot_idx))
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assert hasattr(self.regs, 'peek32')
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assert hasattr(self.regs, 'poke32')
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def unreset_qpll(self):
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# new_val = self.regs.peek32(0x0) & ~0x8
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# self.log.trace("Unresetting MMCM, writing value {:X}".format(new_val))
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self.regs.poke32(0x0, 0x7)
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def check_core(self):
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"""
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Verify JESD core returns correct ID
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"""
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self.log.trace("Checking JESD Core...")
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if self.regs.peek32(self.JESD_SIGNATURE_REG) != 0x4A455344:
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raise Exception('JESD Core signature mismatch! Check that core is mapped correctly')
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#if self.regs.peek32(JESD_REVISION_REG) != 0xFF
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#error here for date revision mismatch
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self.log.trace("JESD Core build code: {0}".format(hex(self.regs.peek32(self.JESD_REVISION_REG))))
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self.log.trace("DB Slot #: {}".format( (self.regs.peek32(0x630) & 0x10000) >> 16 ))
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self.log.trace("DB PID: {:X}".format( self.regs.peek32(0x630) & 0xFFFF ))
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return True
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def init_deframer(self):
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" Initialize deframer "
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self.log.trace("Initializing deframer...")
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self.regs.poke32(self.MGT_RECEIVER_CONTROL, 0x2)
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self.regs.poke32(self.MGT_RX_DESCRAMBLER_CONTROL, 0x0)
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self._gt_reset('rx', reset_only=False)
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self.regs.poke32(self.MGT_RECEIVER_CONTROL, 0x0)
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def init_framer(self):
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" Initialize framer "
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self.log.trace("Initializing framer...")
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# Disable DAC Sync from requesting CGS & Stop Deframer
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self.regs.poke32(self.MGT_TRANSMITTER_CONTROL, 0x2002)
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# Reset, unreset, and check the GTs
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self._gt_reset('tx', reset_only=False)
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# MGT phy control... enable TX Driver Swing
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self.regs.poke32(self.MGT_TX_TRANSCEIVER_CONTROL, 0xF0000)
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time.sleep(0.001)
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# Bypass scrambler and disable char replacement
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self.regs.poke32(self.MGT_TX_SCRAMBLER_CONTROL, 0x1)
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# Check for Framer in Idle state
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rb = self.regs.peek32(self.MGT_TRANSMITTER_CONTROL)
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if rb & 0x100 != 0x100:
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raise Exception('TX Framer is not idle after reset')
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# Enable the framer and incoming DAC Sync
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self.regs.poke32(self.MGT_TRANSMITTER_CONTROL, 0x1000)
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self.regs.poke32(self.MGT_TRANSMITTER_CONTROL, 0x0001)
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def get_framer_status(self):
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" Return True if framer is in good status "
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rb = self.regs.peek32(self.MGT_TRANSMITTER_CONTROL)
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self.log.trace("FPGA Framer status: {0}".format(hex(rb & 0xFF0)))
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if rb & (0b1 << 8) == 0b1 << 8:
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self.log.warning("Framer warning: Framer is Idle!")
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elif rb & (0b1 << 6) == 0b0 << 6:
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self.log.warning("Framer warning: Code Group Sync failed to complete!")
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elif rb & (0b1 << 7) == 0b0 << 7:
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self.log.warning("Framer warning: Lane Alignment failed to complete!")
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return rb & 0xFF0 == 0x6C0
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def get_deframer_status(self):
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" Return True if deframer is in good status "
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rb = self.regs.peek32(self.MGT_RECEIVER_CONTROL)
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self.log.trace("FPGA Deframer status: {0}".format(hex(rb & 0xFFFFFFFF)))
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if rb & (0b1 << 2) == 0b0 << 2:
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self.log.warning("Deframer warning: Code Group Sync failed to complete!")
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elif rb & (0b1 << 3) == 0b0 << 3:
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self.log.warning("Deframer warning: Channel Bonding failed to complete!")
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elif rb & (0b1 << 21) == 0b1 << 21:
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self.log.warning("Deframer warning: Misc link error!")
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return rb & 0xFFFFFFFF == 0xF000001C
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def init(self):
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"""
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Initializes to the core. Needs to happen after the clock signal is ready.
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"""
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self.log.trace("Initializing core...")
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self._gt_pll_power_control()
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self._gt_reset('tx', reset_only=True)
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self._gt_reset('rx', reset_only=True)
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self._gt_pll_lock_control()
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# Disable SYSREF Sampler
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self.regs.poke32(self.SYSREF_CAPTURE_CONTROL, 0x9800040)
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def enable_lmfc(self):
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"""
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Enable LMFC generator in FPGA. This step is woefully incomplete, but this call will work for now.
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"""
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self.regs.poke32(self.SYSREF_CAPTURE_CONTROL, 0x9800000)
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def send_sysref_pulse(self):
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"""
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Toggles the LMK pin that triggers a SYSREF pulse.
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Note: SYSREFs must be enabled on LMK separately beforehand.
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"""
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self.log.trace("Sending SYSREF pulse...")
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self.regs.poke32(0x206C, 0x40000000) # Bit 30. Self-clears.
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def _gt_reset(self, tx_or_rx, reset_only=False):
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" Put MGTs into reset. Optionally unresets and enables them "
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assert tx_or_rx.lower() in ('rx', 'tx')
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mgt_reg = {'tx': 0x2020, 'rx': 0x2024}[tx_or_rx]
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self.log.trace("Resetting %s MGTs..." % tx_or_rx.upper())
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self.regs.poke32(mgt_reg, 0x10)
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if not reset_only:
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self.regs.poke32(mgt_reg, 0x20)
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rb = -1
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for _ in range(20):
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rb = self.regs.peek32(mgt_reg)
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if rb & 0xFFFF0000 == 0x000F0000:
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return True
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time.sleep(0.001)
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raise Exception('Timeout in GT {trx} Reset (Readback: 0x{rb:X})'.format(
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trx=tx_or_rx.upper(),
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rb=(rb & 0xFFFF0000),
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))
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return True
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def _gt_pll_power_control(self):
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" Power down unused CPLLs and QPLLs "
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self.log.trace("Powering down unused CPLLs and QPLLs...")
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self.regs.poke32(0x200C, 0xFFF000E)
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def _gt_pll_lock_control(self):
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"""
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Turn on the PLLs we're using, and make sure lock bits are set.
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"""
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self.regs.poke32(0x2000, 0x1111) # Reset QPLLs
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self.regs.poke32(0x2000, 0x1110) # Unreset the ones we're using
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time.sleep(0.002) # alternatively, poll on the locked bit below
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self.regs.poke32(0x2000, 0x10000) # Clear all QPLL sticky bits
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rb = self.regs.peek32(0x2000) # Read QPLL locked and no unlocked stickies.
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self.log.trace("Reading QPLL lock bit: {0}".format(hex(rb & 0xF)))
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# Error: GT PLL failed to lock.
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if rb & 0xF != 0x2:
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raise Exception("GT PLL failed to lock!")
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def reset_mykonos(self):
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" Toggle reset line on Mykonos "
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self.regs.poke32(0x0008, 0) # Active low reset
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time.sleep(0.001)
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self.regs.poke32(0x0008, 1) # No longer in reset
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