mirror of
https://github.com/saymrwulf/uhd.git
synced 2026-05-16 21:10:10 +00:00
ba00ff0cf5
The FSRU (aka EISCAT) was never supported in UHD 4.0. The FPGA repository never had the relevant files, and the block controller also never existed. This removes all the corresponding files from MPM, as well as some references from makefiles.
23 lines
684 B
Python
23 lines
684 B
Python
#
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# Copyright 2017-2018 Ettus Research, a National Instruments Company
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#
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# SPDX-License-Identifier: GPL-3.0-or-later
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#
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"""
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dboards module __init__.py
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"""
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from .base import DboardManagerBase
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from usrp_mpm import __simulated__
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if not __simulated__:
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from .magnesium import Magnesium
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from .rhodium import Rhodium
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from .neon import Neon
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from .e31x_db import E31x_db
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from .empty_slot import EmptySlot
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from .zbx import ZBX
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from .test import test
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from .unknown import unknown
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from .dboard_iface import DboardIface
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from .x4xx_db_iface import X4xxDboardIface
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from .x4xx_debug_db import X4xxDebugDboard
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from .x4xx_if_test_cca import X4xxIfTestCCA
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