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The FSRU (aka EISCAT) was never supported in UHD 4.0. The FPGA repository never had the relevant files, and the block controller also never existed. This removes all the corresponding files from MPM, as well as some references from makefiles. |
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|---|---|---|
| .. | ||
| pyusrp_periphs | ||
| tests | ||
| usrp_mpm | ||
| aurora_bist_test.py | ||
| CMakeLists.txt | ||
| copy_python_module.cmake | ||
| e320_bist | ||
| n3xx_bist | ||
| setup.py.in | ||
| socket_test.py | ||
| test_lmk.py | ||
| usrp_hwd.py | ||
| usrp_update_fs | ||
| x4xx_bist | ||