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https://github.com/saymrwulf/uhd.git
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2a575bf9b5
Co-authored-by: Lars Amsel <lars.amsel@ni.com> Co-authored-by: Michael Auchter <michael.auchter@ni.com> Co-authored-by: Martin Braun <martin.braun@ettus.com> Co-authored-by: Paul Butler <paul.butler@ni.com> Co-authored-by: Cristina Fuentes <cristina.fuentes-curiel@ni.com> Co-authored-by: Humberto Jimenez <humberto.jimenez@ni.com> Co-authored-by: Virendra Kakade <virendra.kakade@ni.com> Co-authored-by: Lane Kolbly <lane.kolbly@ni.com> Co-authored-by: Max Köhler <max.koehler@ni.com> Co-authored-by: Andrew Lynch <andrew.lynch@ni.com> Co-authored-by: Grant Meyerhoff <grant.meyerhoff@ni.com> Co-authored-by: Ciro Nishiguchi <ciro.nishiguchi@ni.com> Co-authored-by: Thomas Vogel <thomas.vogel@ni.com>
263 lines
10 KiB
Python
263 lines
10 KiB
Python
#
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# Copyright 2021 Ettus Research, a National Instruments Brand
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#
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# SPDX-License-Identifier: GPL-3.0-or-later
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#
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"""
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X4xx RFDC register control
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"""
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import time
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from usrp_mpm.sys_utils.uio import UIO
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class RfdcRegsControl:
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"""
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Control the FPGA RFDC registers external to the XRFdc API
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"""
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# pylint: disable=bad-whitespace
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IQ_SWAP_OFFSET = 0x10000
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MMCM_RESET_BASE_OFFSET = 0x11000
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RF_RESET_CONTROL_OFFSET = 0x12000
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RF_RESET_STATUS_OFFSET = 0x12008
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RF_STATUS_OFFSET = 0x13000
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FABRIC_DSP_INFO_OFFSET = 0x13008
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CAL_DATA_OFFSET = 0x14000
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CAL_ENABLE_OFFSET = 0x14008
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THRESHOLD_STATUS_OFFSET = 0x15000
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RF_PLL_CONTROL_OFFSET = 0x16000
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RF_PLL_STATUS_OFFSET = 0x16008
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# pylint: enable=bad-whitespace
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def __init__(self, label, log):
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self.log = log.getChild("RfdcRegs")
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self.regs = UIO(
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label=label,
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read_only=False
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)
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self.poke32 = self.regs.poke32
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self.peek32 = self.regs.peek32
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# Index corresponds to dboard number.
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self._converter_chains_in_reset = True
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def get_threshold_status(self, slot_id, channel, threshold_idx):
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"""
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Retrieves the status bit for the given threshold block
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"""
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BITMASKS = {
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(0, 0, 0): 0x04,
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(0, 0, 1): 0x08,
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(0, 1, 0): 0x01,
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(0, 1, 1): 0x02,
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(1, 0, 0): 0x400,
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(1, 0, 1): 0x800,
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(1, 1, 0): 0x100,
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(1, 1, 1): 0x200,
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}
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assert (slot_id, channel, threshold_idx) in BITMASKS
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status = self.peek(self.THRESHOLD_STATUS_OFFSET)
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status_bool = (status & BITMASKS[(slot_id, channel, threshold_idx)]) != 0
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return 1 if status_bool else 0
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def set_cal_data(self, i, q):
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assert 0 <= i < 2**16
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assert 0 <= q < 2**16
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self.poke(self.CAL_DATA_OFFSET, (q << 16) | i)
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def set_cal_enable(self, channel, enable):
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assert 0 <= channel <= 3
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assert enable in [False, True]
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en = self.peek(self.CAL_ENABLE_OFFSET)
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bit_offsets = {
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0: 0,
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1: 1,
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2: 4,
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3: 5,
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}
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en_mask = 1 << bit_offsets[channel]
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en = en & ~en_mask
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self.poke(self.CAL_ENABLE_OFFSET, en | (en_mask if enable else 0))
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def enable_iq_swap(self, enable, db_id, block_id, is_dac):
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iq_swap_bit = (int(is_dac) * 8) + (db_id * 4) + block_id
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# Write IQ swap bit with a mask
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reg_val = self.peek(self.IQ_SWAP_OFFSET)
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reg_val = (reg_val & ~(1 << iq_swap_bit)) \
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| (enable << iq_swap_bit)
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self.poke(self.IQ_SWAP_OFFSET, reg_val)
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def set_reset_mmcm(self, reset=True):
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if reset:
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# Put the MMCM in reset (active low)
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self.poke(self.MMCM_RESET_BASE_OFFSET, 0)
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else:
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# Take the MMCM out of reset
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self.poke(self.MMCM_RESET_BASE_OFFSET, 1)
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def wait_for_mmcm_locked(self, timeout=0.001):
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"""
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Wait for MMCM to come to a stable locked state.
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The datasheet specifies a 100us max lock time
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"""
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DATA_CLK_PLL_LOCKED = 1 << 20
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POLL_SLEEP = 0.0002
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for _ in range(int(timeout / POLL_SLEEP)):
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time.sleep(POLL_SLEEP)
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status = self.peek(self.RF_PLL_STATUS_OFFSET)
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if status & DATA_CLK_PLL_LOCKED:
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self.log.trace("RF MMCM lock detected.")
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return
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self.log.error("MMCM failed to lock in the expected time.")
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raise RuntimeError("MMCM failed to lock within the expected time.")
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def set_gated_clock_enables(self, value=True):
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"""
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Controls the clock enable for data_clk and
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data_clk_2x
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"""
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ENABLE_DATA_CLK = 1
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ENABLE_DATA_CLK_2X = 1 << 4
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ENABLE_RF_CLK = 1 << 8
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ENABLE_RF_CLK_2X = 1 << 12
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if value:
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# Enable buffers gating the clocks
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self.poke(self.RF_PLL_CONTROL_OFFSET,
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ENABLE_DATA_CLK |
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ENABLE_DATA_CLK_2X |
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ENABLE_RF_CLK |
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ENABLE_RF_CLK_2X
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)
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else:
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# Disable clock buffers to have clocks gated.
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self.poke(self.RF_PLL_CONTROL_OFFSET, 0)
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def get_fabric_dsp_info(self, dboard):
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"""
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Read the DSP information register and returns the
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DSP bandwidth, rx channel count and tx channel count
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"""
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# Offsets
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DSP_BW = 0 + 16*dboard
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DSP_RX_CNT = 12 + 16*dboard
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DSP_TX_CNT = 14 + 16*dboard
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# Masks
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DSP_BW_MSK = 0xFFF
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DSP_RX_CNT_MSK = 0x3
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DSP_TX_CNT_MSK = 0x3
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dsp_info = self.peek(self.FABRIC_DSP_INFO_OFFSET)
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self.log.trace("Fabric DSP for dboard %d...", dboard)
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dsp_bw = (dsp_info >> DSP_BW) & DSP_BW_MSK
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self.log.trace(" Bandwidth (MHz): %d", dsp_bw)
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dsp_rx_cnt = (dsp_info >> DSP_RX_CNT) & DSP_RX_CNT_MSK
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self.log.trace(" Rx channel count: %d", dsp_rx_cnt)
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dsp_tx_cnt = (dsp_info >> DSP_TX_CNT) & DSP_TX_CNT_MSK
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self.log.trace(" Tx channel count: %d", dsp_tx_cnt)
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return [dsp_bw, dsp_rx_cnt, dsp_tx_cnt]
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def get_rfdc_resampling_factor(self, dboard):
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"""
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Returns the appropriate decimation/interpolation factor to set in the RFDC.
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"""
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# DSP vs. RFDC decimation/interpolation dictionary
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# Key: bandwidth in MHz
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# Value: (RFDC resampling factor, is Half-band resampling used?)
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RFDC_RESAMPLING_FACTOR = {
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100: (8, False), # 100 MHz BW requires 8x RFDC resampling
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200: (2, True), # 200 MHz BW requires 2x RFDC resampling
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# (400 MHz RFDC DSP used w/ half-band resampling)
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400: (2, False) # 400 MHz BW requires 2x RFDC resampling
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}
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dsp_bw, _, _ = self.get_fabric_dsp_info(dboard)
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# When no RF fabric DSP is present (dsp_bw = 0), MPM should
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# simply use the default RFDC resampling factor (400 MHz).
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if dsp_bw in RFDC_RESAMPLING_FACTOR:
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rfdc_resampling_factor, halfband = RFDC_RESAMPLING_FACTOR[dsp_bw]
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else:
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rfdc_resampling_factor, halfband = RFDC_RESAMPLING_FACTOR[400]
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self.log.trace(" Using default resampling!")
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self.log.trace(" RFDC resampling: %d", rfdc_resampling_factor)
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return (rfdc_resampling_factor, halfband)
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def set_reset_adc_dac_chains(self, reset=True):
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""" Resets or enables the ADC and DAC chain for the given dboard """
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def _wait_for_done(done_bit, timeout=5):
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"""
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Wait for the specified sequence done bit when resetting or
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enabling an ADC or DAC chain. Throws an error on timeout.
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"""
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status = self.peek(self.RF_RESET_STATUS_OFFSET)
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if (status & done_bit):
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return
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for _ in range(0, timeout):
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time.sleep(0.001) # 1 ms
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status = self.peek(self.RF_RESET_STATUS_OFFSET)
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if (status & done_bit):
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return
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self.log.error("Timeout while resetting or enabling ADC/DAC chains.")
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raise RuntimeError("Timeout while resetting or enabling ADC/DAC chains.")
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# CONTROL OFFSET
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ADC_RESET = 1 << 4
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DAC_RESET = 1 << 8
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# STATUS OFFSET
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ADC_SEQ_DONE = 1 << 7
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DAC_SEQ_DONE = 1 << 11
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if reset:
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if self._converter_chains_in_reset:
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self.log.debug('Converters are already in reset. '
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'The reset bit will NOT be toggled.')
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return
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# Reset the ADC and DAC chains
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self.log.trace('Resetting ADC chain')
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self.poke(self.RF_RESET_CONTROL_OFFSET, ADC_RESET)
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_wait_for_done(ADC_SEQ_DONE)
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self.poke(self.RF_RESET_CONTROL_OFFSET, 0x0)
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self.log.trace('Resetting DAC chain')
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self.poke(self.RF_RESET_CONTROL_OFFSET, DAC_RESET)
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_wait_for_done(DAC_SEQ_DONE)
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self.poke(self.RF_RESET_CONTROL_OFFSET, 0x0)
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self._converter_chains_in_reset = True
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else: # enable
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self._converter_chains_in_reset = False
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def log_status(self):
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status = self.peek(self.RF_STATUS_OFFSET)
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self.log.debug("Daughterboard 0")
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self.log.debug(" @RFDC")
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self.log.debug(" DAC(1:0) TREADY : {:02b}".format((status >> 0) & 0x3))
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self.log.debug(" DAC(1:0) TVALID : {:02b}".format((status >> 2) & 0x3))
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self.log.debug(" ADC(1:0) I TREADY : {:02b}".format((status >> 6) & 0x3))
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self.log.debug(" ADC(1:0) I TVALID : {:02b}".format((status >> 10) & 0x3))
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self.log.debug(" ADC(1:0) Q TREADY : {:02b}".format((status >> 4) & 0x3))
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self.log.debug(" ADC(1:0) Q TVALID : {:02b}".format((status >> 8) & 0x3))
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self.log.debug(" @USER")
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self.log.debug(" ADC(1:0) OUT TVALID: {:02b}".format((status >> 12) & 0x3))
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self.log.debug(" ADC(1:0) OUT TREADY: {:02b}".format((status >> 14) & 0x3))
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self.log.debug("Daughterboard 1")
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self.log.debug(" @RFDC")
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self.log.debug(" DAC(1:0) TREADY : {:02b}".format((status >> 16) & 0x3))
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self.log.debug(" DAC(1:0) TVALID : {:02b}".format((status >> 18) & 0x3))
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self.log.debug(" ADC(1:0) I TREADY : {:02b}".format((status >> 22) & 0x3))
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self.log.debug(" ADC(1:0) I TVALID : {:02b}".format((status >> 26) & 0x3))
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self.log.debug(" ADC(1:0) Q TREADY : {:02b}".format((status >> 20) & 0x3))
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self.log.debug(" ADC(1:0) Q TVALID : {:02b}".format((status >> 24) & 0x3))
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self.log.debug(" @USER")
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self.log.debug(" ADC(1:0) OUT TVALID: {:02b}".format((status >> 28) & 0x3))
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self.log.debug(" ADC(1:0) OUT TREADY: {:02b}".format((status >> 30) & 0x3))
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def poke(self, addr, val):
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with self.regs:
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self.regs.poke32(addr, val)
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def peek(self, addr):
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with self.regs:
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result = self.regs.peek32(addr)
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return result
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