mirror of
https://github.com/saymrwulf/uhd.git
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2a575bf9b5
Co-authored-by: Lars Amsel <lars.amsel@ni.com> Co-authored-by: Michael Auchter <michael.auchter@ni.com> Co-authored-by: Martin Braun <martin.braun@ettus.com> Co-authored-by: Paul Butler <paul.butler@ni.com> Co-authored-by: Cristina Fuentes <cristina.fuentes-curiel@ni.com> Co-authored-by: Humberto Jimenez <humberto.jimenez@ni.com> Co-authored-by: Virendra Kakade <virendra.kakade@ni.com> Co-authored-by: Lane Kolbly <lane.kolbly@ni.com> Co-authored-by: Max Köhler <max.koehler@ni.com> Co-authored-by: Andrew Lynch <andrew.lynch@ni.com> Co-authored-by: Grant Meyerhoff <grant.meyerhoff@ni.com> Co-authored-by: Ciro Nishiguchi <ciro.nishiguchi@ni.com> Co-authored-by: Thomas Vogel <thomas.vogel@ni.com>
780 lines
35 KiB
Python
780 lines
35 KiB
Python
#
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# Copyright 2021 Ettus Research, a National Instruments Company
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#
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# SPDX-License-Identifier: GPL-3.0-or-later
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#
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"""
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X400 Clocking Management
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This module handles the analog clocks on the X4x0 motherboard. The clocking
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architecture of the motherboard is spread out between a clocking auxiliary board,
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which contains a GPS-displicined OCXO, but also connects an external reference
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to the motherboard. It also houses a PLL for deriving a clock from the network
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(eCPRI). The clocking aux board has its own control class (ClockingAuxBrdControl)
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which also contains controls for the eCPRI PLL.
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The motherboard itself has two main PLLs for clocking purposes: The Sample PLL
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(also SPLL) is used to create all clocks used for RF-related purposes. It creates
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the sample clock (a very fast clock, ~3 GHz) and the PLL reference clock (PRC)
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which is used as a timebase for the daughterboard CPLD and a reference for the
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LO synthesizers (50-64 MHz).
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Its input is the base reference clock (BRC). This clock comes either from the
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clocking aux board, which in turn can provide a reference from the OCXO (with or
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without GPS-disciplining) or from the external reference input SMA port.
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The BRC is typically 10-25 MHz.
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The BRC can also come from the reference PLL (RPLL), when the clock source is
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set to 'mboard'. The RPLL produces clocks that are consumed by the GTY banks
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(for Ethernet and Aurora), but it can also generate a reference clock for
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the SPLL. By default, its reference is a fixed 100 MHz clock, but it can also be
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driven by the eCPRI PLL, which itself can be driven by a clock from the GTY banks,
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which is the case if the clock source is set to 'nsync'.
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The master clock rate (MCR) is not actually controlled in this module, but it
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depends on the sample clock rate. It also depends on the RFDC settings, so it is
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controlled in x4xx.py, which has access to both RFDC and X4xxClockMgr.
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Block diagram (for more details, see the schematic)::
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┌────────────────────────────────────────────────────────┐
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│ Clocking Aux Board │
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│ ┌────────┐ ┌────────┐ ┌────────┐ ┌────────┐ │
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│ │ GPSDO ├─> OCXO │ │External│ │eCPRI/ │ │
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│ │ │ │ │ │ │ │nsync │ │
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│ └────────┘ └────┬───┘ └───┬────┘ └────────┘ │
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│ │ │ │
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│ │ │ │
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│ ┌───────────v─────────v───┐ ┌───────────┐ │
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│ │ │ │eCPRI PLL │ │
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│ └┐ MUX ┌┘ │LMK05318 │ │
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│ └─┐ ┌─┘ │ │ │
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│ └─┬─────────────────┘ └──┬────────┘ │
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│ │ │ │
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└───────────┼───────────────────────────┼────────────────┘
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│ │
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│ ┌─────────────┐ │
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┌──v──v┐ │ │
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│ MUX │ │ │ ┌───── 100 MHz
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└──┬───┘ │ │ │
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│Base Ref. Clock │ │ │
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┌───────v───────┐ │ ┌───────v──v──┐
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│ Sample PLL │ └──┤Reference PLL│
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│ LMK04832 │ │LMK03328 │
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│ │ │ │
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│ │ │ │
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└──┬─────────┬──┘ └────┬────────┘
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│ │ │
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│ │ │
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v v v
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Sample PLL Reference GTY Banks
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Clock Clock
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The code in this module controls the RPLL and SPLL as well as some of the muxing.
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The eCPRI PLL is controlled from the ClockingAuxBrdControl class.
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Most importantly, this class controls the sequencing of configuring clocks. This
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means it won't only switch muxes and configure PLLs, but will also do things in
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the right order, and put components in reset where necessary.
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For this reason, it requires callbacks to reset RFDC and daughterboard clocks.
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"""
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from enum import Enum
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from usrp_mpm import lib # Pulls in everything from C++-land
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from usrp_mpm.sys_utils import i2c_dev
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from usrp_mpm.sys_utils.gpio import Gpio
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from usrp_mpm.sys_utils.udev import dt_symbol_get_spidev
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from usrp_mpm.periph_manager.x4xx_periphs import MboardRegsControl
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from usrp_mpm.periph_manager.x4xx_sample_pll import LMK04832X4xx
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from usrp_mpm.periph_manager.x4xx_reference_pll import LMK03328X4xx
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from usrp_mpm.periph_manager.x4xx_clk_aux import ClockingAuxBrdControl
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from usrp_mpm.mpmutils import poll_with_timeout
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from usrp_mpm.rpc_server import no_rpc
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# this is not the frequency out of the GPSDO(GPS Lite, 20MHz) itself but
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# the GPSDO on the CLKAUX board is used to fine tune the OCXO via EFC
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# which is running at 10MHz
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X400_GPSDO_OCXO_CLOCK_FREQ = 10e6
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X400_RPLL_I2C_LABEL = 'rpll_i2c'
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X400_DEFAULT_RPLL_REF_SOURCE = '100M_reliable_clk'
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X400_DEFAULT_MGT_CLOCK_RATE = 156.25e6
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X400_DEFAULT_INT_CLOCK_FREQ = 25e6
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class X4xxClockMgr:
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"""
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X4x0 Clocking Manager
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The clocking subsystem of X4x0 is very complex. This class is designed to
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capture all clocking-related logic specific to the X4x0.
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This class controls clock and time sources.
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"""
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CLOCK_SOURCE_MBOARD = "mboard"
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CLOCK_SOURCE_INTERNAL = ClockingAuxBrdControl.SOURCE_INTERNAL
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CLOCK_SOURCE_EXTERNAL = ClockingAuxBrdControl.SOURCE_EXTERNAL
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CLOCK_SOURCE_GPSDO = ClockingAuxBrdControl.SOURCE_GPSDO
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CLOCK_SOURCE_NSYNC = ClockingAuxBrdControl.SOURCE_NSYNC
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TIME_SOURCE_INTERNAL = "internal"
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TIME_SOURCE_EXTERNAL = "external"
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TIME_SOURCE_GPSDO = "gpsdo"
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TIME_SOURCE_QSFP0 = "qsfp0"
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# All valid sync_sources for X4xx in the form of (clock_source, time_source)
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valid_sync_sources = {
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(CLOCK_SOURCE_MBOARD, TIME_SOURCE_INTERNAL),
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(CLOCK_SOURCE_INTERNAL, TIME_SOURCE_INTERNAL),
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(CLOCK_SOURCE_EXTERNAL, TIME_SOURCE_EXTERNAL),
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(CLOCK_SOURCE_EXTERNAL, TIME_SOURCE_INTERNAL),
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(CLOCK_SOURCE_GPSDO, TIME_SOURCE_GPSDO),
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(CLOCK_SOURCE_GPSDO, TIME_SOURCE_INTERNAL),
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(CLOCK_SOURCE_NSYNC, TIME_SOURCE_INTERNAL),
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}
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class SetSyncRetVal(Enum):
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OK = 'OK'
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NOP = 'nop'
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FAIL = 'failure'
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def __init__(self,
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clock_source,
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time_source,
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ref_clock_freq,
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sample_clock_freq,
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is_legacy_mode,
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clk_aux_board,
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cpld_control,
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log):
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# Store parent objects
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self.log = log.getChild("ClkMgr")
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self._cpld_control = cpld_control
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self._clocking_auxbrd = clk_aux_board
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self._time_source = time_source
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self._clock_source = clock_source
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self._int_clock_freq = X400_DEFAULT_INT_CLOCK_FREQ
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self._ext_clock_freq = ref_clock_freq
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# Preallocate other objects to satisfy linter
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self.mboard_regs_control = None
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self._sample_pll = None
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self._reference_pll = None
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self._rpll_i2c_bus = None
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self._base_ref_clk_select = None
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self._set_reset_rfdc = lambda **kwargs: None
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self._set_reset_db_clocks = lambda *args: None
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self._rpll_reference_sources = {}
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# Init peripherals
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self._init_available_srcs()
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self._init_clk_peripherals()
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# Now initialize the clocks themselves
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self._init_ref_clock_and_time(
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clock_source,
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ref_clock_freq,
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sample_clock_freq,
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is_legacy_mode,
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)
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self._init_meas_clock()
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self._cpld_control.enable_pll_ref_clk()
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###########################################################################
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# Initialization code
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###########################################################################
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def _init_available_srcs(self):
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"""
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Initialize the available clock and time sources.
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"""
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has_gps = self._clocking_auxbrd and self._clocking_auxbrd.is_gps_supported()
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self._avail_clk_sources = [self.CLOCK_SOURCE_MBOARD]
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if self._clocking_auxbrd:
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self._avail_clk_sources.extend([
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self.CLOCK_SOURCE_INTERNAL,
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self.CLOCK_SOURCE_EXTERNAL])
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if self._clocking_auxbrd.is_nsync_supported():
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self._avail_clk_sources.append(self.CLOCK_SOURCE_NSYNC)
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if has_gps:
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self._avail_clk_sources.append(self.CLOCK_SOURCE_GPSDO)
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self.log.trace(f"Available clock sources are: {self._avail_clk_sources}")
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self._avail_time_sources = [
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self.TIME_SOURCE_INTERNAL, self.TIME_SOURCE_EXTERNAL, self.TIME_SOURCE_QSFP0]
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if has_gps:
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self._avail_time_sources.append(self.TIME_SOURCE_GPSDO)
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self.log.trace("Available time sources are: {}".format(self._avail_time_sources))
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def _init_clk_peripherals(self):
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"""
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Initialize objects for peripherals owned by this class. Most importantly,
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this includes the RPLL and SPLL control classes.
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"""
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# Create SPI and I2C interfaces to the LMK registers
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spll_spi_node = dt_symbol_get_spidev('spll')
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sample_lmk_regs_iface = lib.spi.make_spidev_regs_iface(
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spll_spi_node,
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1000000, # Speed (Hz)
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0x3, # SPI mode
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8, # Addr shift
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0, # Data shift
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1<<23, # Read flag
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0, # Write flag
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)
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# Initialize I2C connection to RPLL
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self._rpll_i2c_bus = i2c_dev.dt_symbol_get_i2c_bus(X400_RPLL_I2C_LABEL)
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if self._rpll_i2c_bus is None:
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raise RuntimeError("RPLL I2C bus could not be found")
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reference_lmk_regs_iface = lib.i2c.make_i2cdev_regs_iface(
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self._rpll_i2c_bus,
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0x54, # addr
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False, # ten_bit_addr
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100, # timeout_ms
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1 # reg_addr_size
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)
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self._sample_pll = LMK04832X4xx(sample_lmk_regs_iface, self.log)
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self._reference_pll = LMK03328X4xx(reference_lmk_regs_iface, self.log)
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# Init BRC select GPIO control
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self._base_ref_clk_select = Gpio('BASE-REFERENCE-CLOCK-SELECT', Gpio.OUTPUT, 1)
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def _init_ref_clock_and_time(self,
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clock_source,
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ref_clock_freq,
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sample_clock_freq,
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is_legacy_mode,
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):
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"""
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Initialize clock and time sources. After this function returns, the
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reference signals going to the FPGA are valid.
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This is only called once, during __init__(). Calling it again will set
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clocks to defaults, but is also redundant since clocks do not need to be
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initialized twice.
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"""
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# A dictionary of tuples (source #, rate) corresponding to each
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# available RPLL reference source.
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# source # 1 => PRIREF source
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# source # 2 => SECREF source
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self._rpll_reference_sources = {X400_DEFAULT_RPLL_REF_SOURCE: (2, 100e6)}
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reference_rates = [None, None]
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for source, rate in self._rpll_reference_sources.values():
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reference_rates[source-1] = rate
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self._reference_pll.reference_rates = reference_rates
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# Now initializes and reconfigure all clocks.
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# If clock_source and ref_clock_freq are not provided, they will not be changed.
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# If any other parameters are not provided, they will be configured with
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# default values.
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self._reset_clocks(value=True, reset_list=['cpld'])
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if clock_source is not None:
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self._set_brc_source(clock_source)
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if ref_clock_freq is not None:
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self._set_ref_clock_freq(ref_clock_freq)
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self._config_rpll(
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X400_DEFAULT_MGT_CLOCK_RATE,
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X400_DEFAULT_INT_CLOCK_FREQ,
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X400_DEFAULT_RPLL_REF_SOURCE)
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self._config_spll(sample_clock_freq, is_legacy_mode)
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self._reset_clocks(value=False, reset_list=['cpld'])
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def _init_meas_clock(self):
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"""
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Initialize the TDC measurement clock. After this function returns, the
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FPGA TDC meas_clock is valid.
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"""
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# This may or may not be used for X400. Leave as a place holder
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self.log.debug("TDC measurement clock not yet implemented.")
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###########################################################################
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# Public APIs (that are not exposed as MPM calls)
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###########################################################################
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@no_rpc
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def set_rfdc_reset_cb(self, rfdc_reset_cb):
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"""
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Set reference to RFDC control. Ideally, we'd get that in __init__(), but
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due to order of operations, it's not ready yet when we call that.
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"""
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self._set_reset_rfdc = rfdc_reset_cb
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@no_rpc
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def set_dboard_reset_cb(self, db_reset_cb):
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"""
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Set reference to RFDC control. Ideally, we'd get that in __init__(), but
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due to order of operations, it's not ready yet when we call that.
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"""
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self._set_reset_db_clocks = db_reset_cb
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@no_rpc
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def unset_cbs(self):
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"""
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Removes any stored references to our owning X4xx class instance
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"""
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self._set_reset_rfdc = None
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self._set_reset_db_clocks = None
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@no_rpc
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def config_pps_to_timekeeper(self, master_clock_rate):
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""" Configures the path from the PPS to the timekeeper"""
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pps_source = "internal_pps" \
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if self._time_source == self.TIME_SOURCE_INTERNAL \
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else "external_pps"
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self._sync_spll_clocks(pps_source)
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self._configure_pps_forwarding(True, master_clock_rate)
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@no_rpc
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def get_clock_sources(self):
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"""
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Lists all available clock sources.
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"""
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return self._avail_clk_sources
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@no_rpc
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def get_time_sources(self):
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" Returns list of valid time sources "
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return self._avail_time_sources
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@no_rpc
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def get_ref_clock_freq(self):
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" Returns the currently active reference clock frequency (BRC) "
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clock_source = self.get_clock_source()
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if clock_source == self.CLOCK_SOURCE_MBOARD:
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return self._int_clock_freq
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if clock_source == self.CLOCK_SOURCE_GPSDO:
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return X400_GPSDO_OCXO_CLOCK_FREQ
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# clock_source == "external":
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return self._ext_clock_freq
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@no_rpc
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def get_ref_locked(self):
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"""
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Return lock status both RPLL and SPLL.
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"""
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ref_pll_status = self._reference_pll.get_status()
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sample_pll_status = self._sample_pll.get_status()
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return all([
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ref_pll_status['PLL1 lock'],
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ref_pll_status['PLL2 lock'],
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sample_pll_status['PLL1 lock'],
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sample_pll_status['PLL2 lock'],
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])
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@no_rpc
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def set_spll_rate(self, sample_clock_freq, is_legacy_mode):
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"""
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Safely set the output rate of the sample PLL.
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This will do the required resets.
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"""
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self._reset_clocks(value=True, reset_list=('rfdc', 'cpld', 'db_clock'))
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self._config_spll(sample_clock_freq, is_legacy_mode)
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self._reset_clocks(value=False, reset_list=('rfdc', 'cpld', 'db_clock'))
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@no_rpc
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def set_sync_source(self, clock_source, time_source):
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"""
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Selects reference clock and PPS sources. Unconditionally re-applies the
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time source to ensure continuity between the reference clock and time
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rates.
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Note that if we change the source such that the time source is changed
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to 'external', then we need to also disable exporting the reference
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clock (RefOut and PPS-In are the same SMA connector).
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"""
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assert (clock_source, time_source) in self.valid_sync_sources, \
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f'Clock and time source pair ({clock_source}, {time_source}) is ' \
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'not a valid selection'
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# Now see if we can keep the current settings, or if we need to run an
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# update of sync sources:
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if (clock_source == self._clock_source) and (time_source == self._time_source):
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spll_status = self._sample_pll.get_status()
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rpll_status = self._reference_pll.get_status()
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if (spll_status['PLL1 lock'] and spll_status['PLL2 lock'] and
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rpll_status['PLL1 lock'] and rpll_status['PLL2 lock']):
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# Nothing change no need to do anything
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self.log.trace("New sync source assignment matches "
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"previous assignment. Ignoring update command.")
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return self.SetSyncRetVal.NOP
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self.log.debug(
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"Although the clock source has not changed, some PLLs "
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"are not locked. Setting clock source again...")
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self.log.trace("- SPLL status: {}".format(spll_status))
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self.log.trace("- RPLL status: {}".format(rpll_status))
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# Start setting sync source
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self.log.debug(
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f"Setting sync source to time_source={time_source}, "
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f"clock_source={clock_source}")
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self._time_source = time_source
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# Reset downstream clocks (excluding RPLL)
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self._reset_clocks(value=True, reset_list=('db_clock', 'cpld', 'rfdc', 'spll'))
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self._set_brc_source(clock_source)
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return self.SetSyncRetVal.OK
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@no_rpc
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def set_clock_source_out(self, enable=True):
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"""
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Allows routing the clock configured as source on the clk aux board to
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the RefOut terminal. This only applies to internal, gpsdo and nsync.
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"""
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clock_source = self.get_clock_source()
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if self.get_time_source() == self.TIME_SOURCE_EXTERNAL:
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raise RuntimeError(
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'Cannot export clock when using external time reference!')
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if clock_source not in self._clocking_auxbrd.VALID_CLK_EXPORTS:
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raise RuntimeError(f"Invalid source to export: `{clock_source}'")
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if self._clocking_auxbrd is None:
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raise RuntimeError("No clocking aux board available")
|
|
return self._clocking_auxbrd.export_clock(enable)
|
|
|
|
###########################################################################
|
|
# Top-level BIST APIs
|
|
#
|
|
# These calls will be available as MPM calls. They are only needed by BIST.
|
|
###########################################################################
|
|
def enable_ecpri_clocks(self, enable=True, clock='both'):
|
|
"""
|
|
Enable or disable the export of FABRIC and GTY_RCV eCPRI
|
|
clocks. Main use case until we support eCPRI is manufacturing
|
|
testing.
|
|
"""
|
|
self.mboard_regs_control.enable_ecpri_clocks(enable, clock)
|
|
|
|
def nsync_change_input_source(self, source):
|
|
"""
|
|
Switches the input reference source of the clkaux lmk (the "eCPRI PLL").
|
|
|
|
Valid options are: fabric_clk, gty_rcv_clk, and sec_ref.
|
|
|
|
fabric_clk and gty_rcv_clk are clock sources from the mboard.
|
|
They are both inputs to the primary reference source of the clkaux lmk.
|
|
sec_ref is the default reference select for the clkaux lmk, it has
|
|
two inputs: Ref in or internal and GPS mode
|
|
|
|
Only a public API for the BIST.
|
|
"""
|
|
assert source in (
|
|
self._clocking_auxbrd.SOURCE_NSYNC_LMK_PRI_FABRIC_CLK,
|
|
self._clocking_auxbrd.SOURCE_NSYNC_LMK_PRI_GTY_RCV_CLK,
|
|
self._clocking_auxbrd.NSYNC_SEC_REF,
|
|
)
|
|
if source == self._clocking_auxbrd.SOURCE_NSYNC_LMK_PRI_FABRIC_CLK:
|
|
self.enable_ecpri_clocks(True, 'fabric')
|
|
self._clocking_auxbrd.set_nsync_ref_select(
|
|
self._clocking_auxbrd.NSYNC_PRI_REF)
|
|
self._clocking_auxbrd.set_nsync_pri_ref_source(source)
|
|
elif source == self._clocking_auxbrd.SOURCE_NSYNC_LMK_PRI_GTY_RCV_CLK:
|
|
self.enable_ecpri_clocks(True, 'gty_rcv')
|
|
self._clocking_auxbrd.set_nsync_ref_select(
|
|
self._clocking_auxbrd.NSYNC_PRI_REF)
|
|
self._clocking_auxbrd.set_nsync_pri_ref_source(source)
|
|
else:
|
|
self._clocking_auxbrd.set_nsync_ref_select(
|
|
self._clocking_auxbrd.NSYNC_SEC_REF)
|
|
|
|
def config_rpll_to_nsync(self):
|
|
"""
|
|
Configures the rpll to use the LMK28PRIRefClk output
|
|
by the clkaux LMK
|
|
"""
|
|
# LMK28PRIRefClk only available when nsync is source, as lmk
|
|
# is powered off otherwise
|
|
self.set_sync_source(clock_source='nsync', time_source=self._time_source)
|
|
|
|
# Add LMK28PRIRefClk as an available RPLL reference source
|
|
# 1 => PRIREF source; source is output at 25 MHz
|
|
# TODO: enable out4 on LMK
|
|
previous_ref_rate = self._reference_pll.reference_rates[0]
|
|
self._rpll_reference_sources['clkaux_nsync_clk'] = (1, 25e6)
|
|
self._reference_pll.reference_rates[0] = 25e6
|
|
self._config_rpll(X400_DEFAULT_MGT_CLOCK_RATE,
|
|
X400_DEFAULT_INT_CLOCK_FREQ,
|
|
'clkaux_nsync_clk')
|
|
|
|
# remove clkaux_nsync_clk as a valid reference source for later calls
|
|
# to _config_rpll(), it is only valid in this configuration
|
|
self._reference_pll.reference_rates[0] = previous_ref_rate
|
|
del self._rpll_reference_sources['clkaux_nsync_clk']
|
|
|
|
def get_fpga_aux_ref_freq(self):
|
|
"""
|
|
Return the tick count of an FPGA counter which measures the width of
|
|
the PPS signal on the FPGA_AUX_REF FPGA input using a 40 MHz clock.
|
|
Main use case until we support eCPRI is manufacturing testing.
|
|
A return value of 0 indicates absence of a valid PPS signal on the
|
|
FPGA_AUX_REF line.
|
|
"""
|
|
return self.mboard_regs_control.get_fpga_aux_ref_freq()
|
|
|
|
###########################################################################
|
|
# Top-level APIs
|
|
#
|
|
# These calls will be available as MPM calls
|
|
###########################################################################
|
|
def get_clock_source(self):
|
|
" Return the currently selected clock source "
|
|
return self._clock_source
|
|
|
|
def get_time_source(self):
|
|
" Return the currently selected time source "
|
|
return self._time_source
|
|
|
|
def get_spll_freq(self):
|
|
""" Returns the output frequency setting of the SPLL """
|
|
return self._sample_pll.output_freq
|
|
|
|
def get_prc_rate(self):
|
|
"""
|
|
Returns the rate of the PLL Reference Clock (PRC) which is
|
|
routed to the daughterboards.
|
|
Note: The ref clock will change if the sample clock frequency
|
|
is modified.
|
|
"""
|
|
prc_clock_map = {
|
|
2.94912e9: 61.44e6,
|
|
3e9: 62.5e6,
|
|
# 3e9: 50e6, RF Legacy mode will be checked separately
|
|
3.072e9: 64e6,
|
|
}
|
|
|
|
# RF Legacy Mode always has a PRC rate of 50 MHz
|
|
if self._sample_pll.is_legacy_mode:
|
|
return 50e6
|
|
# else:
|
|
return prc_clock_map[self.get_spll_freq()]
|
|
|
|
def set_ref_clk_tuning_word(self, tuning_word, out_select=0):
|
|
"""
|
|
Set the tuning word for the clocking aux board DAC. This wull update the
|
|
tuning word used by the DAC.
|
|
"""
|
|
if self._clocking_auxbrd is not None:
|
|
self._clocking_auxbrd.config_dac(tuning_word, out_select)
|
|
else:
|
|
raise RuntimeError("No clocking aux board available")
|
|
|
|
def get_ref_clk_tuning_word(self, out_select=0):
|
|
"""
|
|
Get the tuning word configured for the clocking aux board DAC.
|
|
"""
|
|
if self._clocking_auxbrd is None:
|
|
raise RuntimeError("No clocking aux board available")
|
|
return self._clocking_auxbrd.read_dac(out_select)
|
|
|
|
def store_ref_clk_tuning_word(self, tuning_word):
|
|
"""
|
|
Store the given tuning word in the clocking aux board ID EEPROM.
|
|
"""
|
|
if self._clocking_auxbrd is not None:
|
|
self._clocking_auxbrd.store_tuning_word(tuning_word)
|
|
else:
|
|
raise RuntimeError("No clocking aux board available")
|
|
|
|
def get_sync_sources(self):
|
|
"""
|
|
Enumerates permissible sync sources.
|
|
"""
|
|
return [{
|
|
"time_source": time_source,
|
|
"clock_source": clock_source
|
|
} for (clock_source, time_source) in self.valid_sync_sources]
|
|
|
|
|
|
###########################################################################
|
|
# Low-level controls
|
|
###########################################################################
|
|
def _reset_clocks(self, value, reset_list):
|
|
"""
|
|
Shuts down all clocks downstream to upstream or clears reset on all
|
|
clocks upstream to downstream. Specify the list of clocks to reset in
|
|
reset_list. The order of clocks specified in the reset_list does not
|
|
affect the order in which the clocks are reset.
|
|
"""
|
|
if value:
|
|
self.log.trace("Reset clocks: {}".format(reset_list))
|
|
if 'db_clock' in reset_list:
|
|
self._set_reset_db_clocks(value)
|
|
if 'cpld' in reset_list:
|
|
self._cpld_control.enable_pll_ref_clk(enable=False)
|
|
if 'rfdc' in reset_list:
|
|
self._set_reset_rfdc(reset=True)
|
|
if 'spll' in reset_list:
|
|
self._sample_pll.reset(value, hard=True)
|
|
if 'rpll' in reset_list:
|
|
self._reference_pll.reset(value, hard=True)
|
|
else:
|
|
self.log.trace("Bring clocks out of reset: {}".format(reset_list))
|
|
if 'rpll' in reset_list:
|
|
self._reference_pll.reset(value, hard=True)
|
|
if 'spll' in reset_list:
|
|
self._sample_pll.reset(value, hard=True)
|
|
if 'rfdc' in reset_list:
|
|
self._set_reset_rfdc(reset=False)
|
|
if 'cpld' in reset_list:
|
|
self._cpld_control.enable_pll_ref_clk(enable=True)
|
|
if 'db_clock' in reset_list:
|
|
self._set_reset_db_clocks(value)
|
|
|
|
def _config_rpll(self, usr_clk_rate, internal_brc_rate, internal_brc_source):
|
|
"""
|
|
Configures the LMK03328 to generate the desired MGT reference clocks
|
|
and internal BRC rate.
|
|
|
|
Currently, the MGT protocol selection is not supported, but a custom
|
|
usr_clk_rate can be generated from PLL1.
|
|
|
|
usr_clk_rate - the custom clock rate to generate from PLL1
|
|
internal_brc_rate - the rate to output as the BRC
|
|
internal_brc_source - the reference source which drives the RPLL
|
|
"""
|
|
if internal_brc_source not in self._rpll_reference_sources:
|
|
self.log.error('Invalid internal BRC source of {} was selected.'
|
|
.format(internal_brc_source))
|
|
raise RuntimeError('Invalid internal BRC source of {} was selected.'
|
|
.format(internal_brc_source))
|
|
ref_select = self._rpll_reference_sources[internal_brc_source][0]
|
|
|
|
# If the desired rate matches the rate of the primary reference source,
|
|
# directly passthrough that reference source
|
|
if internal_brc_rate == self._reference_pll.reference_rates[0]:
|
|
brc_select = 'bypass'
|
|
else:
|
|
brc_select = 'PLL'
|
|
self._reference_pll.init()
|
|
self._reference_pll.config(
|
|
ref_select, internal_brc_rate, usr_clk_rate, brc_select)
|
|
# The internal BRC rate will only change when _config_rpll is called
|
|
# with a new internal BRC rate
|
|
self._int_clock_freq = internal_brc_rate
|
|
|
|
def _config_spll(self, sample_clock_freq, is_legacy_mode):
|
|
"""
|
|
Configures the SPLL for the specified master clock rate.
|
|
"""
|
|
self._sample_pll.init()
|
|
self._sample_pll.config(sample_clock_freq, self.get_ref_clock_freq(),
|
|
is_legacy_mode)
|
|
|
|
def _set_brc_source(self, clock_source):
|
|
"""
|
|
Switches the Base Reference Clock Source between internal, external,
|
|
mboard, and gpsdo using the GPIO pin and clocking aux board control.
|
|
internal is a clock source internal to the clocking aux board, but
|
|
external to the motherboard.
|
|
Should not be called outside of set_sync_source or _init_ref_clock_and_time
|
|
without proper reset and reconfig of downstream clocks.
|
|
"""
|
|
if clock_source == self.CLOCK_SOURCE_MBOARD:
|
|
self._base_ref_clk_select.set(1)
|
|
if self._clocking_auxbrd:
|
|
self._clocking_auxbrd.export_clock(False)
|
|
else:
|
|
if self._clocking_auxbrd is None:
|
|
self.log.error('Invalid BRC selection {}. No clocking aux '
|
|
'board was found.'.format(clock_source))
|
|
raise RuntimeError('Invalid BRC selection {}'.format(clock_source))
|
|
self._base_ref_clk_select.set(0)
|
|
if clock_source == self.CLOCK_SOURCE_EXTERNAL:
|
|
# This case is a bit special: We also need to tell the clocking
|
|
# aux board if we plan to consume the external time reference or
|
|
# not.
|
|
time_src_board = \
|
|
ClockingAuxBrdControl.SOURCE_EXTERNAL \
|
|
if self._time_source == self.TIME_SOURCE_EXTERNAL \
|
|
else ClockingAuxBrdControl.SOURCE_INTERNAL
|
|
self._clocking_auxbrd.set_source(
|
|
ClockingAuxBrdControl.SOURCE_EXTERNAL, time_src_board)
|
|
elif clock_source == self.CLOCK_SOURCE_INTERNAL:
|
|
self._clocking_auxbrd.set_source(ClockingAuxBrdControl.SOURCE_INTERNAL)
|
|
elif clock_source == self.CLOCK_SOURCE_GPSDO:
|
|
self._clocking_auxbrd.set_source(ClockingAuxBrdControl.SOURCE_GPSDO)
|
|
elif clock_source == self.CLOCK_SOURCE_NSYNC:
|
|
self._clocking_auxbrd.set_source(ClockingAuxBrdControl.SOURCE_NSYNC)
|
|
else:
|
|
self.log.error('Invalid BRC selection {}'.format(clock_source))
|
|
raise RuntimeError('Invalid BRC selection {}'.format(clock_source))
|
|
self._clock_source = clock_source
|
|
self.log.debug(f"Base reference clock source is: {clock_source}")
|
|
|
|
def _sync_spll_clocks(self, pps_source="internal_pps"):
|
|
"""
|
|
Synchronize base reference clock (BRC) and PLL reference clock (PRC)
|
|
at start of PPS trigger.
|
|
|
|
Uses the LMK 04832 pll1_r_divider_sync to synchronize BRC with PRC.
|
|
This sync method uses a callback to actual trigger the sync. Before
|
|
the trigger is pulled (CLOCK_CTRL_PLL_SYNC_TRIGGER) PPS source is
|
|
configured base on current reference clock and pps_source. After sync
|
|
trigger the method waits for 1sec for the CLOCK_CTRL_PLL_SYNC_DONE
|
|
to go high.
|
|
|
|
:param pps_source: select whether internal ("internal_pps") or external
|
|
("external_pps") PPS should be used. This parameter
|
|
is taken into account when the current clock source
|
|
is external. If the current clock source is set to
|
|
internal then this parameter is not taken into
|
|
account.
|
|
:return: success state of sync call
|
|
:raises RuntimeError: for invalid combinations of reference clock and
|
|
pps_source
|
|
"""
|
|
def select_pps():
|
|
"""
|
|
Select PPS source based on current clock source and pps_source.
|
|
|
|
This returns the bits for the motherboard CLOCK_CTRL register that
|
|
control the PPS source.
|
|
"""
|
|
EXT_PPS = "external_pps"
|
|
INT_PPS = "internal_pps"
|
|
PPS_SOURCES = (EXT_PPS, INT_PPS)
|
|
assert pps_source in PPS_SOURCES, \
|
|
"%s not in %s" % (pps_source, PPS_SOURCES)
|
|
|
|
supported_configs = {
|
|
(10E6, EXT_PPS): MboardRegsControl.CLOCK_CTRL_PPS_EXT,
|
|
(10E6, INT_PPS): MboardRegsControl.CLOCK_CTRL_PPS_INT_10MHz,
|
|
(25E6, INT_PPS): MboardRegsControl.CLOCK_CTRL_PPS_INT_25MHz
|
|
}
|
|
|
|
config = (self.get_ref_clock_freq(), pps_source)
|
|
if config not in supported_configs:
|
|
raise RuntimeError("Unsupported combination of reference clock "
|
|
"(%.2E) and PPS source (%s) for PPS sync." %
|
|
config)
|
|
return supported_configs[config]
|
|
|
|
return self._sample_pll.pll1_r_divider_sync(
|
|
lambda: self.mboard_regs_control.pll_sync_trigger(select_pps()))
|
|
|
|
def _configure_pps_forwarding(self, enable, master_clock_rate, delay=1.0):
|
|
"""
|
|
Configures the PPS forwarding to the sample clock domain (master
|
|
clock rate). This function assumes _sync_spll_clocks function has
|
|
already been executed.
|
|
|
|
:param enable: Boolean to choose whether PPS is forwarded to the
|
|
sample clock domain.
|
|
|
|
:param delay: Delay in seconds from the PPS rising edge to the edge
|
|
occurence in the application. This value has to be in
|
|
range 0 < x <= 1. In order to forward the PPS signal
|
|
from base reference clock to sample clock an aligned
|
|
rising edge of the clock is required. This can be
|
|
created by the _sync_spll_clocks function. Based on the
|
|
greatest common divisor of the two clock rates there
|
|
are multiple occurences of an aligned edge each second.
|
|
One of these aligned edges has to be chosen for the
|
|
PPS forwarding by setting this parameter.
|
|
|
|
:return: None, Exception on error
|
|
"""
|
|
return self.mboard_regs_control.configure_pps_forwarding(
|
|
enable, master_clock_rate, self.get_prc_rate(), delay)
|
|
|
|
def _set_ref_clock_freq(self, freq):
|
|
"""
|
|
Tell our USRP what the frequency of the external reference clock is.
|
|
|
|
Will throw if it's not a valid value.
|
|
"""
|
|
if (freq < 1e6) or (freq > 50e6):
|
|
raise RuntimeError('External reference clock frequency is out of the valid range.')
|
|
if (freq % 40e3) != 0:
|
|
# TODO: implement exception of a 50e3 step size for 200MSPS
|
|
raise RuntimeError('External reference clock frequency is of incorrect step size.')
|
|
self._ext_clock_freq = freq
|
|
# If the external source is currently selected we also need to re-apply the
|
|
# time_source. This call also updates the dboards' rates.
|
|
if self.get_clock_source() == self.CLOCK_SOURCE_EXTERNAL:
|
|
self.set_sync_source(self._clock_source, self._time_source)
|