9 commits

Author	SHA1	Message	Date
Ashish Chaudhari	41657ecc53	ad9361: Cleaned up constants and macros	2014-08-13 10:29:31 -07:00
Ashish Chaudhari	9ad16ae70e	ad9361: Converted stdint types to boost types	2014-08-12 18:51:29 -07:00
Ashish Chaudhari	675350a1d6	b200, ad9361: Cleanup up AD9361 driver ... - Removed transaction interface - Made the driver a C++ class	2014-08-12 18:28:36 -07:00
Ashish Chaudhari	c7274790a0	b200: Moved AD9361 driver to host ... - Switched to FPGA SPI engine - Moved firmware AD9361 driver to UHD - Bumped FW compat to 5, FPGA compat to 4 - Known Issue: AD9361 SPI rate is too slow	2014-08-01 13:14:56 -07:00
Balint Seeber	da99b7edc2	b200: changed ad9361 ctrl/transaction magic number 64 to macro, as it is in the FX3 FW	2014-03-19 16:19:46 -07:00
Balint Seeber	383128e2c9	b200: throw exception when master clock rate (tick rate) is requested to be > max for certain # of channels (i.e. restrict to 30.72MHz for MIMO) ... Also includes sscanf type fix in b200_impl and longer timeout for AD9361 read	2014-02-14 15:40:30 -08:00
Josh Blum	9c3fd67181	b200: lower clock rate is 5MHz due to DCM	2013-08-16 10:49:03 -07:00
Josh Blum	d251a7a55b	b200: use existing query rate calls to clip	2013-07-19 14:45:24 -07:00
Josh Blum	bb73a21495	uhd: squashed support modules for usrp3 fpga cores	2013-07-19 14:00:32 -07:00