Commit graph

4774 commits

Author SHA1 Message Date
Martin Braun
d88ae533c4 Merge branch 'maint' 2014-09-01 17:35:24 +02:00
Nicholas Corgan
db35bf46a5 x300_dboard_iface: added UHD_UNUSED() macro to unused parameters in set_clock_enabled()
* Removes GCC warning about unused parameters
2014-08-29 07:37:03 -07:00
Martin Braun
c3acbb871b Merge branch 'maint' 2014-08-27 09:48:23 +02:00
Martin Braun
6d99396a83 uhd: Added a stop stream cmd to the rx example 2014-08-27 09:48:13 +02:00
Martin Braun
5ffc835e2e uhd: Added a stop stream cmd to the rx example 2014-08-25 22:05:07 +02:00
Ashish Chaudhari
a9b927b53f uhd: Changed line endings from Windows -> UNIX 2014-08-21 15:03:24 -07:00
Ashish Chaudhari
1a778ba733 ad9361: Output PLL lock status on ctrl output pins. 2014-08-21 14:33:55 -07:00
Martin Braun
9d4167d9e2 uhd: Updated images URL and MD5 2014-08-21 23:05:49 +02:00
Martin Braun
8aa4a2d633 Merge branch 'maint'
Conflicts:
	host/CMakeLists.txt
2014-08-21 11:31:55 +02:00
Martin Braun
4514cd2b48 b100: More RX buffers
Increases number of recv frames where recv_frame_size is min'd with 2K
(B100_MAX_PKT_BYTE_LIMIT), therefore increasing buffer slack.
2014-08-21 11:26:07 +02:00
Ashish Chaudhari
25f67e01ae fixup! uhd: updated images url for UHD 3.7.2 release 2014-08-20 14:33:06 -07:00
Ashish Chaudhari
7ec59dab6f uhd: updated images url for UHD 3.7.2 release 2014-08-20 12:21:41 -07:00
Nicholas Corgan
2de96cd57c OctoClock: bugfixes/improvements
* Fixed Ethernet initialization problem
* Improved external reference detection
* Added gratuitous ARP, sent upon power-up
* Tweaked host-side timing for initialization and firmware burning
* Fixed logic for dealing with firmware incompatibility
* Misc efficiency/reliability improvements to firmware's network code
2014-08-20 09:42:26 -07:00
Ashish Chaudhari
9fb6c2919a fpga: Added FPGA code for B200 AD9361 host driver addition 2014-08-20 09:31:33 -07:00
Ashish Chaudhari
72eae05033 Merge branch 'master' into ashish/cat_refactor_phase2 2014-08-20 09:06:32 -07:00
Ashish Chaudhari
d31ffb2ef8 Merge branch 'maint' 2014-08-19 12:09:05 -07:00
Ashish Chaudhari
3347e831f0 fpga: Added FPGA code for X300 MIMO alignment bugfix 2014-08-19 12:05:46 -07:00
Martin Braun
a38fee789d Updated CHANGELOG for 3.7.2rc2 2014-08-18 23:36:02 +02:00
Martin Braun
83249208bd Merge branch 'maint' 2014-08-18 23:05:48 +02:00
michael-west
9bf965c804 Bumping FPGA compat to 7. 2014-08-18 22:52:53 +02:00
michael-west
63794de468 Changed analog delay on DAC reference and radio clocks from 1075ps to 900ps 2014-08-18 22:52:53 +02:00
michael-west
8055ac0d4f - Fixes for channel alignment
- Added analog delay for radio clock
	- Added analog delay for DAC reference clocks
	- Removed resetting of clock control
	- Removed setting of reference clock and PPS to external sources during initialization
- Fixes for set_time_unknown_pps
	- Removed wait for PPS edge after setting time from GPSDO
	- Changed set_time_unknonw_pps to time out based on system time rather than device VITA time
2014-08-18 22:52:53 +02:00
Martin Braun
90fd966e25 Merge branch 'maint' 2014-08-18 13:38:04 +02:00
Nicholas Corgan
7297ebffc3 cmake: fixed FindORC logic, was allowing usage of versions below minimum 2014-08-14 07:05:16 -07:00
Nicholas Corgan
e3826b1a67 Restoring compatibility with CMake 2.6
* The UNSET command didn't exist back then, but using SET with no value does the same thing
* CMake 2.6 doesn't like nested parantheses in IF statements, so tweak IF/ELSE statements
2014-08-14 06:45:53 -07:00
Ashish Chaudhari
505c1d84fa ad9361: Fixed MSVC build issues 2014-08-13 17:16:33 -07:00
Ashish Chaudhari
628826f549 ad9361: Fixed debug messages with UHD_LOGs 2014-08-13 13:12:20 -07:00
Ashish Chaudhari
282b31cedd ad9361: Fixed TX direction bug in ad9361_ctrl 2014-08-13 11:04:23 -07:00
Ashish Chaudhari
09898c18f4 ad9361: Added synchronization to IO and device classes 2014-08-13 10:40:39 -07:00
Ashish Chaudhari
41657ecc53 ad9361: Cleaned up constants and macros 2014-08-13 10:29:31 -07:00
Ashish Chaudhari
302dfa7ea7 Merge remote-tracking branch 'origin/master' into ashish/cat_refactor_phase2 2014-08-12 19:10:42 -07:00
Ashish Chaudhari
b2a246a39d ad9361: Cleaned up errors and debug messages 2014-08-12 19:09:44 -07:00
Ashish Chaudhari
9ad16ae70e ad9361: Converted stdint types to boost types 2014-08-12 18:51:29 -07:00
Ashish Chaudhari
f999fe6552 ad9361: Renamed ad9361_impl.c to ad9361_device.cpp 2014-08-12 18:31:46 -07:00
Ashish Chaudhari
675350a1d6 b200, ad9361: Cleanup up AD9361 driver
- Removed transaction interface
- Made the driver a C++ class
2014-08-12 18:28:36 -07:00
Ashish Chaudhari
145f1d7cf7 b200: Removed all AD9361 related firmware
- FX3 does not respond to AD9361 firmware transaction VREQs
- FX3 does not respond to AD9361 SPI transaction VREQs
- Deleted all AD9361 firmware files
- Bumped FW compat to 6
2014-08-12 11:19:22 -07:00
Ben Hilburn
94c2740bc0 docs: fixing broken doxygen syntax in some existing docs 2014-08-12 12:09:04 +02:00
Ben Hilburn
de12fae1c9 docs: adding page for NIRIO kernel driver install, linking to it 2014-08-12 12:09:04 +02:00
Ashish Chaudhari
96d1d58673 Merge remote-tracking branch 'origin/master' into ashish/cat_refactor_master 2014-08-11 15:57:05 -07:00
Ashish Chaudhari
cce90d3d9b octoclock: Fixed merge conflict. Utils compile now. 2014-08-07 10:10:23 -07:00
Martin Braun
28bc48ee49 Merge branch 'maint' 2014-08-07 17:26:03 +02:00
Ashish Chaudhari
64c1d64901 Merge branch 'master' into ashish/cat_refactor_master 2014-08-05 17:07:46 -07:00
Nicholas Corgan
781d7a24ab cmake: add UHD version to NSIS installer title 2014-08-05 10:29:16 -07:00
Ashish Chaudhari
db6f3a2d7a b200: Added variable rate SPI core for AD9361 and ADF4001
- Added b200_local_spi core that adjusts the divider when talking to the two chips
- AD9361 rate is 1MHz and ADF4001 rate is 10kHz
2014-08-01 16:29:34 -07:00
Ashish Chaudhari
ef5abde4f0 b200: AD9361 firmware bugfixes
- Fix for BUG #485:  B200: Channels Swap Between Runs
  # Added code to transition state machine out of FDD while reconfiguring active chains.
  # bb:0b9929 Mon Jun 16 14:56:26 2014 -0700

- Fix for BUG #500:  B210: RX channels are not phase aligned
  # Set bit to invert RX if internal LNA is bypassed
  # bb:0a4565 Thu Jun 5 17:10:37 2014 -0700
2014-08-01 13:19:41 -07:00
Ashish Chaudhari
c7274790a0 b200: Moved AD9361 driver to host
- Switched to FPGA SPI engine
- Moved firmware AD9361 driver to UHD
- Bumped FW compat to 5, FPGA compat to 4
- Known Issue: AD9361 SPI rate is too slow
2014-08-01 13:14:56 -07:00
Martin Braun
605b470a87 Merge branch 'maint' 2014-08-01 18:11:52 +02:00
Nicholas Corgan
0a0844cf35 Updated master-specfic documentation
* Updated manual URL on OctoClock documentation after manual overhaul
* Improved "Coding to the API" page
2014-07-31 10:49:40 -07:00
Nicholas Corgan
5fc3a5973f Updated documentation
* Updated UHD documentation-related URL's after manual overhaul
* Updated NI-USRP URL to link to NI-USRP 1.3
2014-07-31 10:49:34 -07:00
Martin Braun
4999b5df50 Merge branch 'maint'
Conflicts:
	host/utils/usrp_burn_mb_eeprom.cpp
2014-07-31 15:25:22 +02:00