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4774 commits 30 branches 147 tags 147 MiB
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72 commits

Author SHA1 Message Date
Ashish Chaudhari
72eae05033 Merge branch 'master' into ashish/cat_refactor_phase2 2014-08-20 09:06:32 -07:00
Martin Braun
83249208bd Merge branch 'maint' 2014-08-18 23:05:48 +02:00
michael-west
8055ac0d4f - Fixes for channel alignment 
- Added analog delay for radio clock
	- Added analog delay for DAC reference clocks
	- Removed resetting of clock control
	- Removed setting of reference clock and PPS to external sources during initialization
- Fixes for set_time_unknown_pps
	- Removed wait for PPS edge after setting time from GPSDO
	- Changed set_time_unknonw_pps to time out based on system time rather than device VITA time
 2014-08-18 22:52:53 +02:00
Ashish Chaudhari
41657ecc53 ad9361: Cleaned up constants and macros 2014-08-13 10:29:31 -07:00
Ashish Chaudhari
675350a1d6 b200, ad9361: Cleanup up AD9361 driver 
- Removed transaction interface
- Made the driver a C++ class
 2014-08-12 18:28:36 -07:00
Ashish Chaudhari
145f1d7cf7 b200: Removed all AD9361 related firmware 
- FX3 does not respond to AD9361 firmware transaction VREQs
- FX3 does not respond to AD9361 SPI transaction VREQs
- Deleted all AD9361 firmware files
- Bumped FW compat to 6
 2014-08-12 11:19:22 -07:00
Ashish Chaudhari
64c1d64901 Merge branch 'master' into ashish/cat_refactor_master 2014-08-05 17:07:46 -07:00
Ashish Chaudhari
db6f3a2d7a b200: Added variable rate SPI core for AD9361 and ADF4001 
- Added b200_local_spi core that adjusts the divider when talking to the two chips
- AD9361 rate is 1MHz and ADF4001 rate is 10kHz
 2014-08-01 16:29:34 -07:00
Ashish Chaudhari
c7274790a0 b200: Moved AD9361 driver to host 
- Switched to FPGA SPI engine
- Moved firmware AD9361 driver to UHD
- Bumped FW compat to 5, FPGA compat to 4
- Known Issue: AD9361 SPI rate is too slow
 2014-08-01 13:14:56 -07:00
Martin Braun
4999b5df50 Merge branch 'maint' 
Conflicts:
	host/utils/usrp_burn_mb_eeprom.cpp
 2014-07-31 15:25:22 +02:00
michael-west
35fc42f9fc Merge branch 'maint' into uhd/bug492 
Conflicts:
	host/lib/usrp/b200/b200_impl.cpp
 2014-07-30 11:54:26 -07:00
Nicholas Corgan
a6e18604be OctoClock firmware upgrade, added host driver 
* OctoClock can communicate with UHD over Ethernet
* Can read NMEA strings from GPSDO and send to host
* Added multi_usrp_clock class for clock devices
* uhd::device can now filter to return only USRP devices or clock devices
* New OctoClock bootloader can accept firmware download over Ethernet
* Added octoclock_burn_eeprom,octoclock_firmware_burner utilities
* Added test_clock_synch example to show clock API
 2014-07-23 07:37:32 -07:00
Ben Hilburn
0efddecd45 Merge branch 'origin/b200/bug516' into maint 
Fixing B200 clock rate float compare.
 2014-07-17 18:01:42 -07:00
Ben Hilburn
4e8512abf8 Merge branch 'origin/b200/bug512' into maint 
B200 now creates internal PPS. Depends on FPGA change.
 2014-07-17 17:49:09 -07:00
michael-west
487e7fc2b4 BUG #516: B210: Fails to Run with 30.72 MHz Clock 
- Addressed feedback from review.
 2014-07-10 14:37:38 -07:00
michael-west
bca5edb579 Fix for BUG #492: UHD: set_time_unknown_pps() fails with GPSDO installed 
- Added polling for PPS time change after setting time from GPSDO.
 2014-06-25 14:56:20 -07:00
michael-west
016430b3f8 Fix for BUG #516: B210: Fails to Run with 30.72 MHz Clock 
- Corrected clock rate checks for B2x0
 2014-06-18 13:42:24 -07:00
michael-west
248df215aa Fix for BUG #516: B210: Fails to Run with 30.72 MHz Clock 
- Corrected clock rate checks for B2x0
 2014-06-18 12:43:10 -07:00
michael-west
0db669b3ce Enhancement #512: B210: Need an Internal PPS 
- Added support for internal PPS selection (set as default)
 2014-06-13 11:58:29 -07:00
michael-west
05559d64b9 Fix for BUG #500: B210: RX channels are not phase aligned 
- Adding UHD side code to invert second RX channel
 2014-06-06 15:27:02 -07:00
Ben Hilburn
21518ec2ba Merge branch 'origin/b200/issue_418' 
Fixing unsafe sscanf call.
 2014-04-10 13:09:01 -07:00
Martin Braun
fa996034dd b100+b200+usrp1: removed potentially unsafe sscanf call 2014-04-10 21:36:19 +02:00
Martin Braun
1621df26ac b200: Added max link rate info 2014-04-10 21:03:10 +02:00
Ben Hilburn
f8753a3d7f Merge branch adding warning regarding MCR on the B2xx. 2014-03-27 17:41:13 -07:00
Nicholas Corgan
ff98c2a816 b200: update FPGA loading percentage every 1% instead of 10% 2014-03-27 07:45:32 -07:00
Ben Hilburn
6962543fec Pulling in patch from Marcus Leech for includes and older OSes. 2014-03-26 11:02:11 -07:00
Moritz Fischer
a92d2f8210 b200: Added missing include to b200_impl 
* In order to use std::ceil and std::floor, on older compilers
  we need to still add an include for cmath.

Tested-by: Marcus D. Leech <mleech@ripnet.com>
Signed-off-by: Moritz Fischer <moritz@ettus.com>
 2014-03-23 20:31:26 +01:00
Balint Seeber
da99b7edc2 b200: changed ad9361 ctrl/transaction magic number 64 to macro, as it is in the FX3 FW 2014-03-19 16:19:46 -07:00
Balint Seeber
416c1ff184 b200: explicitly detect libusb timeout 2014-03-19 16:06:28 -07:00
Balint Seeber
ea66e24a96 b200: changed ad9361 read timeout handling (kicks in when requesting master_clock_rate above 56MHz) 2014-03-19 15:53:27 -07:00
Balint Seeber
e898450a2e b200: addressed review comments (boost::uint16_t & source code long line breaking) 2014-03-19 14:33:12 -07:00
Martin Braun
fd1e2f8fc1 b200: Added channel mapping capabilities 2014-02-25 20:20:51 +01:00
Balint Seeber
35a25fb379 Merge branch 'master' of github.com:EttusResearch/uhddev into b200/warn_mimo_mcr 2014-02-20 14:55:53 -08:00
Ashish Chaudhari
a8caec5f93 b200: Fixed bug in rx_dsp_core_3000 that would assume 3 halfbands and X300 settings interface. 2014-02-19 19:22:52 -08:00
Balint Seeber
383128e2c9 b200: throw exception when master clock rate (tick rate) is requested to be > max for certain # of channels (i.e. restrict to 30.72MHz for MIMO) 
Also includes sscanf type fix in b200_impl and longer timeout for AD9361 read
 2014-02-14 15:40:30 -08:00
Ben Hilburn
178ac3f1c9 Merging USRP X300 and X310 support!! 2014-02-04 11:04:07 -08:00
Michael West
dd8e499979 Added timed control commands to test_timed_commands example. Added radio core as subscriber to tick rate change for B200. 2014-01-15 15:09:58 -08:00
Ben Hilburn
4826982ef3 Merging mwest's improvements to B2xx utility. 2013-12-11 18:23:46 -08:00
Ben Hilburn
51de21efd7 Merge of mwest's fix to the sse2_fc32_to_sc16 converter. 2013-12-11 18:01:41 -08:00
Nicholas Corgan
37d3542f9c lib: fixed use of -> to . after switching parameter from pointer to reference 2013-12-03 10:40:23 -08:00
Ben Hilburn
abc682eda8 Final merge of Balint's 'kitchen_sink' B200 fixes. 2013-11-27 15:12:46 -08:00
Ben Hilburn
9e47ad607b Squashed merge of Coverity fixes. 2013-11-27 12:11:23 -08:00
Balint Seeber
7788c69225 b200: fix loopback transfer timeout when operating at USB2 2013-11-20 20:10:14 -08:00
Balint Seeber
58f4af976d b200: check return value from control write of FPGA bitstream for short transfer 2013-11-19 18:41:27 -08:00
Balint Seeber
f568b1984f b200: extra check on loopback request to determine VREQ transfer size 2013-11-19 18:38:15 -08:00
Balint Seeber
aaef714ac5 b200: auto-select VREQ xfer size regardless of FW version 2013-11-19 18:29:24 -08:00
Nicholas Corgan
621f9c93f3 Merge branch 'bug182' 2013-11-19 15:51:45 -08:00
Balint Seeber
465da9a7d3 b200: Reverted RX SPP 2044 -> 2000 (unresolved issue with one app, wait for FPGA bump) 2013-11-19 14:44:18 -08:00
Balint Seeber
48ab2a971e Merge remote-tracking branch 'origin/b200/dtor-master' into b200/kitchen_sink 2013-11-19 13:30:21 -08:00
Johannes Demel
8a78802c10 b200/dtor-stall: final fixes for stall bug 2013-11-19 13:17:52 -08:00