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4774 commits 30 branches 147 tags 147 MiB
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1663 commits

Author SHA1 Message Date
Martin Braun
d88ae533c4 Merge branch 'maint' 2014-09-01 17:35:24 +02:00
Nicholas Corgan
db35bf46a5 x300_dboard_iface: added UHD_UNUSED() macro to unused parameters in set_clock_enabled() 
* Removes GCC warning about unused parameters
 2014-08-29 07:37:03 -07:00
Ashish Chaudhari
a9b927b53f uhd: Changed line endings from Windows -> UNIX 2014-08-21 15:03:24 -07:00
Ashish Chaudhari
1a778ba733 ad9361: Output PLL lock status on ctrl output pins. 2014-08-21 14:33:55 -07:00
Martin Braun
4514cd2b48 b100: More RX buffers 
Increases number of recv frames where recv_frame_size is min'd with 2K
(B100_MAX_PKT_BYTE_LIMIT), therefore increasing buffer slack.
 2014-08-21 11:26:07 +02:00
Ashish Chaudhari
72eae05033 Merge branch 'master' into ashish/cat_refactor_phase2 2014-08-20 09:06:32 -07:00
Martin Braun
83249208bd Merge branch 'maint' 2014-08-18 23:05:48 +02:00
michael-west
9bf965c804 Bumping FPGA compat to 7. 2014-08-18 22:52:53 +02:00
michael-west
63794de468 Changed analog delay on DAC reference and radio clocks from 1075ps to 900ps 2014-08-18 22:52:53 +02:00
michael-west
8055ac0d4f - Fixes for channel alignment 
- Added analog delay for radio clock
	- Added analog delay for DAC reference clocks
	- Removed resetting of clock control
	- Removed setting of reference clock and PPS to external sources during initialization
- Fixes for set_time_unknown_pps
	- Removed wait for PPS edge after setting time from GPSDO
	- Changed set_time_unknonw_pps to time out based on system time rather than device VITA time
 2014-08-18 22:52:53 +02:00
Ashish Chaudhari
505c1d84fa ad9361: Fixed MSVC build issues 2014-08-13 17:16:33 -07:00
Ashish Chaudhari
628826f549 ad9361: Fixed debug messages with UHD_LOGs 2014-08-13 13:12:20 -07:00
Ashish Chaudhari
282b31cedd ad9361: Fixed TX direction bug in ad9361_ctrl 2014-08-13 11:04:23 -07:00
Ashish Chaudhari
09898c18f4 ad9361: Added synchronization to IO and device classes 2014-08-13 10:40:39 -07:00
Ashish Chaudhari
41657ecc53 ad9361: Cleaned up constants and macros 2014-08-13 10:29:31 -07:00
Ashish Chaudhari
b2a246a39d ad9361: Cleaned up errors and debug messages 2014-08-12 19:09:44 -07:00
Ashish Chaudhari
9ad16ae70e ad9361: Converted stdint types to boost types 2014-08-12 18:51:29 -07:00
Ashish Chaudhari
f999fe6552 ad9361: Renamed ad9361_impl.c to ad9361_device.cpp 2014-08-12 18:31:46 -07:00
Ashish Chaudhari
675350a1d6 b200, ad9361: Cleanup up AD9361 driver 
- Removed transaction interface
- Made the driver a C++ class
 2014-08-12 18:28:36 -07:00
Ashish Chaudhari
145f1d7cf7 b200: Removed all AD9361 related firmware 
- FX3 does not respond to AD9361 firmware transaction VREQs
- FX3 does not respond to AD9361 SPI transaction VREQs
- Deleted all AD9361 firmware files
- Bumped FW compat to 6
 2014-08-12 11:19:22 -07:00
Ashish Chaudhari
64c1d64901 Merge branch 'master' into ashish/cat_refactor_master 2014-08-05 17:07:46 -07:00
Ashish Chaudhari
db6f3a2d7a b200: Added variable rate SPI core for AD9361 and ADF4001 
- Added b200_local_spi core that adjusts the divider when talking to the two chips
- AD9361 rate is 1MHz and ADF4001 rate is 10kHz
 2014-08-01 16:29:34 -07:00
Ashish Chaudhari
c7274790a0 b200: Moved AD9361 driver to host 
- Switched to FPGA SPI engine
- Moved firmware AD9361 driver to UHD
- Bumped FW compat to 5, FPGA compat to 4
- Known Issue: AD9361 SPI rate is too slow
 2014-08-01 13:14:56 -07:00
Martin Braun
4999b5df50 Merge branch 'maint' 
Conflicts:
	host/utils/usrp_burn_mb_eeprom.cpp
 2014-07-31 15:25:22 +02:00
michael-west
35fc42f9fc Merge branch 'maint' into uhd/bug492 
Conflicts:
	host/lib/usrp/b200/b200_impl.cpp
 2014-07-30 11:54:26 -07:00
Ben Hilburn
eafae66c03 tx fe corrections: fixing mixed tabs / spaces, other horrible whitespace cruft 2014-07-25 09:44:07 -07:00
Ben Hilburn
9b4def474f Merge 'maint' into x300/bug513 2014-07-25 09:28:19 -07:00
Nicholas Corgan
a6e18604be OctoClock firmware upgrade, added host driver 
* OctoClock can communicate with UHD over Ethernet
* Can read NMEA strings from GPSDO and send to host
* Added multi_usrp_clock class for clock devices
* uhd::device can now filter to return only USRP devices or clock devices
* New OctoClock bootloader can accept firmware download over Ethernet
* Added octoclock_burn_eeprom,octoclock_firmware_burner utilities
* Added test_clock_synch example to show clock API
 2014-07-23 07:37:32 -07:00
michael-west
89b0a915e2 Commented out warning if X300 reference clock fails to lock within 1 second during initialization. Sometimes it takes longer and that is OK. 2014-07-22 15:25:05 -07:00
michael-west
138f1c57db Fix for BUG #517: B200: Regression of power level on RX 
- Fixed scalar for RX DSP core
 2014-07-22 15:15:48 -07:00
Ian Buckley
42b47cea15 X300: Added UHD support for TX FE 2014-07-18 17:15:41 -07:00
michael-west
afb4cb4d4a Updated copyright year. 2014-07-17 18:16:04 -07:00
michael-west
6e740108bf Fix for BUG #469 
- Added mutex for write_uart()
 2014-07-17 18:16:04 -07:00
michael-west
863953d972 - Changed variables from uint8_t to uint32_t so parsing of hex strings would work properly. 2014-07-17 18:16:04 -07:00
michael-west
208d851678 Addressing comments from review. 
- Corrected types of some variables to be boost types.
- Removed debugging code accidentally left in.
- Changed some compiled out error messages to log messages.
 2014-07-17 18:16:04 -07:00
michael-west
8f6e2ac997 Fix for BUG #469: Bad/Empty GPS NMEA strings returned when the queries are made in a random wait iterative fashion 
Fix for BUG #460:  X300: GPGGA sensor most often empty, while RMC is usually OK
- Added checksum verification of NMEA strings
- Improved handling of short or malformed strings
- Fixed GPSDO data synchronization between X300 firmware and host
 2014-07-17 18:16:04 -07:00
Ben Hilburn
0efddecd45 Merge branch 'origin/b200/bug516' into maint 
Fixing B200 clock rate float compare.
 2014-07-17 18:01:42 -07:00
Ben Hilburn
1af6628eb1 Merge branch 'origin/ashish/rx_pcie_overflows' into maint 2014-07-17 17:57:23 -07:00
Ben Hilburn
4e8512abf8 Merge branch 'origin/b200/bug512' into maint 
B200 now creates internal PPS. Depends on FPGA change.
 2014-07-17 17:49:09 -07:00
michael-west
487e7fc2b4 BUG #516: B210: Fails to Run with 30.72 MHz Clock 
- Addressed feedback from review.
 2014-07-10 14:37:38 -07:00
michael-west
24aaac8e3f Fix for BUG #527: N200: 50 Msps results in two tones 
- Adjusted check to enable first half-band filter only if the rate is decimated enough between the CIC and other half-band filter
 2014-07-01 17:11:30 -07:00
Ashish Chaudhari
1bca847406 x300: Bugfix for overflows on PCIe at 200MS/s 2014-06-27 10:50:51 -07:00
michael-west
bca5edb579 Fix for BUG #492: UHD: set_time_unknown_pps() fails with GPSDO installed 
- Added polling for PPS time change after setting time from GPSDO.
 2014-06-25 14:56:20 -07:00
michael-west
016430b3f8 Fix for BUG #516: B210: Fails to Run with 30.72 MHz Clock 
- Corrected clock rate checks for B2x0
 2014-06-18 13:42:24 -07:00
michael-west
248df215aa Fix for BUG #516: B210: Fails to Run with 30.72 MHz Clock 
- Corrected clock rate checks for B2x0
 2014-06-18 12:43:10 -07:00
Ben Hilburn
96c30a11f2 Merge branch 'origin/b200/bug500' into maint - Fixing B200 phase alignment issue 2014-06-16 15:51:27 -07:00
michael-west
0db669b3ce Enhancement #512: B210: Need an Internal PPS 
- Added support for internal PPS selection (set as default)
 2014-06-13 11:58:29 -07:00
michael-west
c884c555be - Changed XOR to OR for REG_DSP_RX_MUX flags. 2014-06-12 11:31:38 -07:00
michael-west
05559d64b9 Fix for BUG #500: B210: RX channels are not phase aligned 
- Adding UHD side code to invert second RX channel
 2014-06-06 15:27:02 -07:00
Ben Hilburn
f2fbcfa30e Lots of bit-specific type work to fix compilation on older OSes. 2014-05-21 11:56:07 -07:00