4 commits

Author	SHA1	Message	Date
Ashish Chaudhari	145f1d7cf7	b200: Removed all AD9361 related firmware ... - FX3 does not respond to AD9361 firmware transaction VREQs - FX3 does not respond to AD9361 SPI transaction VREQs - Deleted all AD9361 firmware files - Bumped FW compat to 6	2014-08-12 11:19:22 -07:00
Ashish Chaudhari	ef5abde4f0	b200: AD9361 firmware bugfixes ... - Fix for BUG #485: B200: Channels Swap Between Runs # Added code to transition state machine out of FDD while reconfiguring active chains. # bb:0b9929 Mon Jun 16 14:56:26 2014 -0700 - Fix for BUG #500: B210: RX channels are not phase aligned # Set bit to invert RX if internal LNA is bypassed # bb:0a4565 Thu Jun 5 17:10:37 2014 -0700	2014-08-01 13:19:41 -07:00
Ashish Chaudhari	c7274790a0	b200: Moved AD9361 driver to host ... - Switched to FPGA SPI engine - Moved firmware AD9361 driver to UHD - Bumped FW compat to 5, FPGA compat to 4 - Known Issue: AD9361 SPI rate is too slow	2014-08-01 13:14:56 -07:00
Ben Hilburn	642f3fb582	b2xx: Pulling FX3 and AD9361 source code into master.	2014-04-07 14:58:25 -07:00