- FX3 does not respond to AD9361 firmware transaction VREQs
- FX3 does not respond to AD9361 SPI transaction VREQs
- Deleted all AD9361 firmware files
- Bumped FW compat to 6
- Fix for BUG #485: B200: Channels Swap Between Runs
# Added code to transition state machine out of FDD while reconfiguring active chains.
# bb:0b9929 Mon Jun 16 14:56:26 2014 -0700
- Fix for BUG #500: B210: RX channels are not phase aligned
# Set bit to invert RX if internal LNA is bypassed
# bb:0a4565 Thu Jun 5 17:10:37 2014 -0700
- Switched to FPGA SPI engine
- Moved firmware AD9361 driver to UHD
- Bumped FW compat to 5, FPGA compat to 4
- Known Issue: AD9361 SPI rate is too slow
* OctoClock can communicate with UHD over Ethernet
* Can read NMEA strings from GPSDO and send to host
* Added multi_usrp_clock class for clock devices
* uhd::device can now filter to return only USRP devices or clock devices
* New OctoClock bootloader can accept firmware download over Ethernet
* Added octoclock_burn_eeprom,octoclock_firmware_burner utilities
* Added test_clock_synch example to show clock API
- Corrected types of some variables to be boost types.
- Removed debugging code accidentally left in.
- Changed some compiled out error messages to log messages.
Fix for BUG #460: X300: GPGGA sensor most often empty, while RMC is usually OK
- Added checksum verification of NMEA strings
- Improved handling of short or malformed strings
- Fixed GPSDO data synchronization between X300 firmware and host
- Restored link state handling.
- Enabled forwarding of packets not addressed to this device's MAC address.
- Kept forwarding of broadcast packets disabled.
NOTE: This is a workaround and not a permanent fix.
- Disabled packet forwarding and link state cycle detection in firmware.
- Fixed the link state algorithm so the updating runs the first time and
the forwading update only happens when necessary.
- Added check for 10GbE before calling MDIO functions.
When an ICMP dest unreachable pkt arrives,
the fw needs to know how to shutoff the DSP.
This offset for the reset register was
broken by a previous fix for register overlap.
1) This should kill any streaming,
the previous calls would just stop continuous streaming
2) The breaks were changed to returns
to avoid reprogramming the framer.
