-Added test cases for the 184.32MHz clock rate.
-Removed some extra test cases for 200MHz clock rate in order to
cut down on test time.
-Added DPDK test cases (copied from 10gige and 2x_10gige test cases).
- Reduce long tests from 3600 seconds to 600 seconds.
- Remove 2xRX@153.6e6 test for N310 10 GbE (not practical).
Signed-off-by: michael-west <michael.west@ettus.com>
- Wait 100ms after a retune before capturing samples. Users can set the
length of time with `--skip-time X`
- Actually set RX gain
- Remove old TODOs
- Print alignment statistics in increasing frequency order
- Fix health check reported values (was reporting radians, but
labeling them as deg)
- Fix calculating the maximum drift for phase differences around
+/-180 degrees
This commit adds FPGA functional verification tests for all the N320
images. The tests follow a similar pattern to N310, but one additional
category is present for using the DPDK transport. In order to use that
test, the use_dpdk and mgmt_addr args must be specified in the options.
This doesn't add any functionality to the phase alignment script, but it
does make the siggen portion pluggable.
Co-authored-by: Brent Stapleton <brent.stapleton@ettus.com>
This tool uses the Python API to determine if USRP devices are
receiving a phase aligned signal. It is designed to be a stand-in
replacement for usrp_phasealignment.py, although the capabilities and
invocation are not identical.
The return value of this tool will indicate whether the signal is
sufficiently phase aligned, and allows integration into scripts or
other test frameworks. This tool also includes options to save data to
file or plot it using PyLab.
Currently only supports 2 channel RX phase alignment.
This tool uses the Python API to acquire a snapshot of samples during
a gain or frequency change. It can be used to analyze the settling time
of analog components, as well as the accuracy in time.
It has two combinable ways of analyzing the data: 1) Write it to a file,
or 2) plot the time-domain data.
Example: This would receive several seconds of data from an X3x0 device,
tune to 1 GHz, and then bump the gain by 30 dB after a set amount of
time:
$ rx_settling_time.py -a type=x300 -f 1e9 -g 0 --new-gain 30 --plot
- Bump the UHD API version and return to development branch status
- Removing artful in list of Ubuntu releases. Support for artful ended
in July 2018.
- new OOT-blocks: phase_calc_ccf hier-block, measurement_sink_f
- new python submodules: flowgraphs, functions, rts_tests
- new apps: usrp_phasealignment.py - cmdline example for manual testing
OOT-Blocks:
- phase_calc_ccf takes two complex input streams and conjugate
multiplys them and extracts the phase from the result and converts
it to degree scale
- measurement_sink_f: takes a float input stream and calculates average and stddev for a
specified number of samples. Start of a measurement is invoked by a
call of start_run() on the block. After a couple of runs average and
stddev can be extracted.
Python modules:
- flowgrahps contains reconfigurable flowgraphs for different GNU
Radio RF test cases
- functions contains functions which are used in different apps/RTS
scripts
- rts_tests contains test cases which are meant to be executed from
the RTS system. Depends on TinyDB, labview_automation
Apps:
- usrp_phasealignment.py is an example how to use the underlying
flowgraph to measure phase differences. Commandline arguments of
uhd_app can be used and several additional arguments can/have to be
specified. Runs a phase difference measurement --runs number of times and averages
phase difference over --duration seconds. Between measurements USRP
sinks are retuned to random frequencies in daughterboard range.
Results are displayed using motherboard serial and daughterboard
serial
