Summary:
This change will allow correct args to pass from mboard to dboards,
that in turn can be useful for dboard manager.
Details:
In N310, the dboard manager needs the time source to be updated before
calling update_ref_clock_source(), because it will trigger a reinit of
the dboard, for which the time_source is essential to determine correct
clock synchronizer settings.
The special case is the white rabbit time source needs a different
internal ref_clock_frequency for the clock synchronizer than the passed
in ref_clock_freq.
Added set_sync_source method to set both the time and clock sources
without forcing a re-init twice. Modified the existing set_time_source
and set_clock_source methods to call into set_sync_source.
- Fix the syntax to open mboard-regs UIO objects, and change the open()
and close() functions to be private.
- We were calling open() twice in every context manager line- once
manually, and once in __enter__. This commit corrects those usages, and
allows the context manager to fully manage the opening and closing of
UIO objects.
Adding the following sensors:
- Catalina temperature, RSSI, and LO Lock sensors
- GPS lock, time, TPV, and SKY sensors
Co-authored-by: Brent Stapleton <brent.stapleton@ettus.com>
When a device is re-initialized without any changes (e.g.,
master_clock_rate, ref_clock_freq) then we can skip the initialization
sequence and move on. This shaves a significant amount of time from the
init sequence.
Fast re-init can be overridden by providing the `force_reinit=1` device
arg.
- Replace mykonos finish_initialization with async version
- Replace myknonos setup_cal with async version
- Remove disable_timeout on rpc_server init()
The log output at level 'INFO' was pretty cluttered. This cleans up the
log messages at the higher levels. In some cases, log message typos or
capitalizations were also fixed.
Add axi_bitq support. In order for this to work we need several
conditions to be true:
- Updated openocd
- FPGA image with axi_bitq built in and hooked up to correct pins
- Updated overlays matching the FPGA image
- An svf file with correct max frequency <= 10MHz
Signed-off-by: Moritz Fischer <moritz.fischer@ettus.com>
Using string expression instead of passing in a total hex value.
Now user can passed in for example: init_cals=DEFAULT or
init_cals=BASIC|TX_QEC_INIT
Reviewed-by: Martin Braun <martin.braun@ettus.com>
Slot A and Slot B are different in how the JESD lanes are connected.
We now pass in different deserializer_lane_xbar config values for each slot.
Reviewed-by: Martin Braun <martin.braun@ettus.com>
Reviewed-by: Daniel Jepson <daniel.jepson@ettus.com>
Reviewed-by: Mark Meserve <mark.meserve@ni.com>
There was a theoretical chance otherwise that we forgot to set the
ref_clock_freq value and it set up the LMK incorrectly.
Reviewed-by: Daniel Jepson <daniel.jepson@ettus.com>
Now checks the oldest-compat-rev register. Current rev is read out for
logging purposes.
Reviewed-by: Daniel Jepson <daniel.jepson@ettus.com>
Reviewed-by: Moritz Fischer <moritz.fischer@ettus.com>
Refactoring to use the C++-based UIO objects. The Liberio and Ethernet
objects now open the UIO before using it, and close it once done.
Reviewed-By: Martin Braun <martin.braun@ettus.com>
