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7 commits

Author SHA1 Message Date
djepson1
4e0600b00a mg: Updated JESD204b init seq and documentation. 
- Based on feedback from ADI, updated SYSREF sequencing for
    meeting deterministic latency requirements.
  - Changed majority of register addresses in nijesdcore.py to
    constants.
  - Corrected write data to SYSREF_CAPTURE_CONTROL to produce
    the correct SYSREF toggle rate inside the FPGA.

Signed-off-by: djepson1 <daniel.jepson@ni.com>
 2017-12-22 15:04:02 -08:00
Daniel Jepson
febfdf27b4 mpm: Minor updates to nijesdcore 
- Better logging
- Better error messages
 2017-12-22 15:04:01 -08:00
DJ Epson
f141f71180 mpm: Streaming-related improvements to Magnesium controls 2017-12-22 15:04:01 -08:00
Martin Braun
6183d9eeaa mpm: Made code Python3-compatible 2017-12-22 15:03:58 -08:00
Mark Meserve
24d3011233 mg: bring up links 2017-12-22 15:03:52 -08:00
Martin Braun
c0fa47a970 n3xx: Moved Mykonos reset to UIO 
Note: This requires a new FPGA image, or Mykonos simply won't reset.
 2017-12-22 15:03:52 -08:00
Martin Braun
b05f72f339 mpm: Added NI JESD core controller 2017-12-22 15:03:45 -08:00