This fixes the behavior that a non-valid dual-rate config could fall
back to a single-rate configuration with two different converter rates.
With this it also fixes the behavior that with those same master clock
rates we wouldn't run mult-tile sync (as this depends on the converter
rate).
Since in dual rate we cannot use multi-tile sync over all tiles we
disable it completely for all tiles. For 1600 MHz bitfiles this isn't an
issue at all because the two remaining channels have different converter
rates anyway. For 400 MHz bitfiles the channels with the same rate will
not be synced, either, but will most probably have a fixed phase
difference.
Co-authored-by: Martin Braun <martin.braun@ettus.com>
- Update X410 and X440 BSP YAML files to properly index clocks
- Update image core files to declare clock indices
- Update get_clocks() in MPM to return the correct values
This does not include changes to the x400_radio_control block registry.
This change by itself will thus not change behaviour.
This change adds a lookup table for the default master clock rate based
on the DSP bandwidth of the FPGA image for X440. Since the default
master clock rate currently is 368.64 MHz and we don't want to change
this for backwards compatibility, we need to have a way to handle lower
bandwidth FPGA images. This is what the LUT provides.
Change the syrnchronization order to be following:
- Run the MTS (multi-tile sync) procedure
- Run the timekeeper alignment to next_pps edge
- Run the post timekeeper alignment steps (none for now)
This ensures that any effects caused due to delay adjustments which are
part of the MTS procedure do not affect timekeeper alignment.
Without this change timekeepers on two X4xx devices would be mis-aligned
slightly in a multi-device scenario.
Note that setting all timekeepers to a common time_spec on the next_pps
as a part of post-initialization application code will still align them perfectly.
Signed-off-by: Virendra Kakade <virendra.kakade@ni.com>
set_clock_source for x440 now errors due to potentially decreased spurious performance, the correct way to change clock source now with a new device initialization
Change all references to "gps_lock" to "gps_locked" for consistency
across the code base. Fixes incorrect use of "gps_lock" for the sensor
name on X4xx.
Signed-off-by: michael-west <michael.west@ettus.com>
To follow Xilinx' recommendations for self-cal usage this adds
startup_tile() to the cal_mode selection and we query if the cal_mode
was set properly. Since we do this, on the host side we allow the full
first Nyquist zone to be used for self-cal.
- Move the configuration of SPLL and MMCM into its own method
- In set_master_clock_rate(), call this with intermediate clock settings
if we decide that going direct from one clock setting to another would
cause harm/failures
Co-authored-by: Martin Braun <martin.braun@ettus.com>
Before this commit, set_sync_source() would require the master clock
rate to be set after reclocking, but would pull it out of the
X4xxClockManager object (using the _master_clock_rates attribute). Now,
the new master clock rate is passed to set_sync_source() via the args
argument.
Note that it is still possible (for backward compat) to not provide
a new MCR, in which case the assumption is that the current MCR still
remains valid.
This avoids unnecessary statefulness of this function and fixes an issue
where during init(), external reference clock frequencies would be
validated against the wrong master clock rates.
This enables querying the converter rate through the sensor API:
```python
>>> U = uhd.usrp.MultiUSRP("type=x4xx")
>>> print(U.get_tx_sensor('rfdc_rate').to_real())
3000000000.0
```
This change ensures that ADC selfcal is triggered during session start
if the clocking was reconfigured. So it saves time if several
consecutive sessions are opened with always the same settings.
It also makes the ADC self cal run if in an open session either
set_clock_source(), set_time_source() or set_sync_source() are called
and a clock reconfiguration was triggered by that.
This changes the default master clock rate for X440 to 368.64 MHz which
results in a converter rate of 2.94912 GSps which is in line with what
X410 uses.
Changes:
- X410 Honors the force_reinit flag now (like N310). When given, it will
force a reinit of all clocking settings.
- When master_clock_rate is not given, and nothing else changes, then
clocking configuration will be skipped. This shaves approx. 3s of
startup time and avoids issues that can occur during clocking
configuration.
- If anything changes, incl. clock/time source, then full clock
configuration is still done.
- Multi-tile sync is done in all cases, as that happens outside of init()
This inherits RuntimeError and saves from logging and throwing in
separate steps. Instead of
```python
log.error("Error X occured!")
raise RuntimeError("Error X occured!")
```
do
```python
raise LogRuntimeError(log, "Error X occured!")
```
This demotes the sync_tiles() error to a warning to be consistent with
what the code does. We only raise a RuntimeError if the tile latencies
are not equal for all tiles, which is a little bit later. This is where
an error log was added now.
sync_tiles() may fail with some rare user configurations but it won't
make the device unusable for all use-cases. Therefore a warning is okay
in that place while bad latencies lead to an error.
This changes the clock-configuration order of operations such that all
SPLL-related settings are applied first (including syncing R-dividers to
PPS), and only then are MMCM and RFDC configured.
Previously, syncing R-dividers would happen after everything was
configured.
This adds an updateable_components overridable dictionary into the
daughterboards base class.
On X410, because some of the FPGA compatibility stems from DB-specific
components, they are moved into class ZBX.
This change fixes issues with the reset strategy for devices that don't
use default clocking parameters. That used to cause issues when
restarting the tiles and made those devices have some bigger variations
in power measurements. For X410 this should not change the behavior
compared to uhd master.
This adds X4xxRfdcCtrl.reset_tiles(), which resets all enabled tiles and
sets their registers and settings back to initial defaults. The same
functionality was previously implemented in reset_rfdc(), but we want to
be able to reset the RFDC clocks without clearing all registers.
During device initialization, however, we retain this reset of all tiles
by modifying the initialization sequence.
Before this change, we indiscriminately first set the sync source in
init(), then the master clock rate again (it is already set in
set_sync_source(), albeit to a potentially older value).
This adds checks to the args to see if things have actually changed, and
sets all settings in one go.
FPGA:
- Split up MB registers that control daughterboard specific settings so
that daughterboards 0 and 1 could have different setings, in
preparation for future devices that require different settings.
This requires a compat number bump to 8.0.
- Add registers for additional RFDC information, including the
block/tile mapping of the individual channels, and information about
resampling capabilities
- Identify sections of code that would be specific to X410/ZBX and move
them to their own headers, so it's trivial to add device-specific
sections of code instead for other devices in the future.
- This includes constraints for clocks and I/O pins.
- Remove ability to do timed ctrlport transactions to the MB CPLD, this
was unused and possibly broken.
- Move daughterboard-specific code into its own code location
(dboards/zbx)
- Move X410-specific register documentation to its own location
(doc/X410)
- Refactor Makefiles to split out X410/ZBX specific components and allow
switching between device types
- Add 512-bit AXI interconnects
- Make number of timekeepers configurable (X410 keeps the single
timekeeper)
MPM:
- Required compat is bumped to 8.0
- Now supports new registers for detecting DSP capabilities and
multi-rate settings for the daughterboards
- Adds MMCM controls (currently unused)
Co-authored-by: Wade Fife <wade.fife@ni.com>
Co-authored-by: Ryan Marlow <ryan@lmarlow.com>
Co-authored-by: Martin Braun <martin.braun@ettus.com>
Co-authored-by: Humberto Jimenez <humberto.jimenez@ni.com>
Resetting MMCM and RFDC separately will become a requirement once we
start to also program the MMCM. As of now, it is merely a refactoring,
and we continue to use default MMCM settings.
- Adds startup_tiles() and shutdown_tiles()
- The latter is called on tear_down() to be compliant with Xilinx'
documentation on bitstream reconfiguration
This is a debugging utility for MPM, where gdb-based debugging sometimes
leads to issues with timing. To use it, replace class instantiations
such as:
```python
c = SomeClass(arg1, arg2)
```
with
```python
c = LogWrapper(
parent_log.getChild("SomeClass"), "info", SomeClass(arg1, arg2))
```
The class can be used as before, but the MPM log will include calls with
arguments, return values, and execution times, like this:
```
[MPM.PeriphManager.rfdcctl] [INFO] set_if(1, 0, True, 1058240000.0)
[MPM.PeriphManager.rfdcctl] [INFO] --> True [Execution time: 0.108 ms]
```
