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This changes the clock-configuration order of operations such that all SPLL-related settings are applied first (including syncing R-dividers to PPS), and only then are MMCM and RFDC configured. Previously, syncing R-dividers would happen after everything was configured. |
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| .. | ||
| pyusrp_periphs | ||
| tests | ||
| usrp_mpm | ||
| aurora_bist_test.py | ||
| CMakeLists.txt | ||
| copy_python_module.cmake | ||
| e320_bist | ||
| n3xx_bist | ||
| setup.py.in | ||
| socket_test.py | ||
| test_lmk.py | ||
| usrp_hwd.py | ||
| usrp_update_fs | ||
| x4xx_bist | ||