Commit graph

10 commits

Author SHA1 Message Date
Martin Braun
876d4150aa uhd: Apply clang-format against all .cpp and .hpp files in host/
Note: template_lvbitx.{cpp,hpp} need to be excluded from the list of
files that clang-format gets applied against.
2020-03-03 08:51:32 -06:00
Sugandha Gupta
002cec940c adf4002: Fixed register programming for power down bit
The bit shift for power down is one off with respect to the
ADF4001/ADF4002 data sheet
2018-04-12 18:41:23 -07:00
Martin Braun
6652eb4a03 uhd: Move internal headers to uhdlib/
To avoid the proliferation of additional include directories and
multiple ways of including project-local headers, we now default to
moving all headers that are used across UHD into the uhdlib/
subdirectory.

Some #include statements were also reordered as they were modified for
closer compliance with the coding guidelines.

Internal cpp source files should now include files like this:

    #include <uhdlib/rfnoc/ctrl_iface.hpp>

Reviewed-by: Ashish Chaudhari <ashish.chaudhari@ettus.com>
2018-03-14 15:17:44 -07:00
Martin Braun
ae5211d71d uhd: Update license headers
All copyright is now attributed to "Ettus Research, a National
Instruments company".

SPDX headers were also updated to latest version 3.0.
2018-02-19 16:54:52 -08:00
Martin Braun
4f948e2c8b Move all license headers to SPDX format. 2017-12-22 10:45:51 -08:00
Andrej Rode
21aad77c9c utils: introduce new logging API and remove msg API 2017-02-20 17:13:15 -08:00
Martin Braun
99c2730bc9 Remove all boost:: namespace prefix for uint32_t, int32_t etc. (fixed-width types)
- Also removes all references to boost/cstdint.hpp and replaces it with
  stdint.h (The 'correct' replacement would be <cstdint>, but not all of our
  compilers support that).
2016-11-08 08:02:22 -08:00
michael-west
10178875a1 ADF4002: Fix register programming (bug #974) 2015-12-15 10:50:39 -08:00
Ashish Chaudhari
db6f3a2d7a b200: Added variable rate SPI core for AD9361 and ADF4001
- Added b200_local_spi core that adjusts the divider when talking to the two chips
- AD9361 rate is 1MHz and ADF4001 rate is 10kHz
2014-08-01 16:29:34 -07:00
Josh Blum
bb73a21495 uhd: squashed support modules for usrp3 fpga cores 2013-07-19 14:00:32 -07:00