bluew 026a98d56a pulp-runtime: Fix uart frequency and bad fll access ... Control-pulp doesn't have an FLL so we hardcode the frequency domain values. Furthermore we allow these hardcoded values to change depending on whether we target the FPGA (zcu102) or rtl sim.		2021-11-04 17:47:57 +01:00
..
chips	pulp-runtime: Fix uart frequency and bad fll access	2021-11-04 17:47:57 +01:00
cluster_ctrl
cv32e40p	target: Add pulpissimo with cv32e40p	2021-07-20 16:03:12 +02:00
dma
eu
fll
gpio
gvsoc
hwme
ibex
itc
riscv	chips/control_pulp: Overhaul header inclusion for control_pulp	2021-07-19 12:14:04 +02:00
soc_eu
stdout
timer
udma	archi,hal: Add udma_hyper	2021-07-13 17:33:00 +02:00
pulp.h
pulp_defs.h
utils.h