mirror of
https://github.com/saymrwulf/pulp-runtime.git
synced 2026-05-31 23:27:54 +00:00
Few fixes
This commit is contained in:
Germain Haugou
parent
cbcdbe22ff
commit
fa62145237
13 changed files with 648 additions and 12 deletions
121
include/archi/chips/pulpissimo/apb_soc.h
Normal file
121
include/archi/chips/pulpissimo/apb_soc.h
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@ -0,0 +1,121 @@
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/*
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* Copyright (C) 2018 ETH Zurich and University of Bologna
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*
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* Licensed under the Apache License, Version 2.0 (the "License");
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* you may not use this file except in compliance with the License.
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* You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS,
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* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*/
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#ifndef __ARCHI_PULPISSIMO_APB_SOC_H__
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#define __ARCHI_PULPISSIMO_APB_SOC_H__
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#define APB_SOC_BOOT_OTHER 0
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#define APB_SOC_BOOT_JTAG 1
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#define APB_SOC_BOOT_SPI 2
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#define APB_SOC_BOOT_ROM 3
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#define APB_SOC_BOOT_PRELOAD 4
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#define APB_SOC_BOOT_HYPER 5
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#define APB_SOC_BOOT_SPIM 6
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#define APB_SOC_BOOT_SPIM_QPI 7
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#define APB_SOC_PLT_OTHER 0
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#define APB_SOC_PLT_FPGA 1
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#define APB_SOC_PLT_RTL 2
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#define APB_SOC_PLT_VP 3
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#define APB_SOC_PLT_CHIP 4
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//PADs configuration is made of 8bits out of which only the first 6 are used
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//bit0 enable pull UP
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//bit1 enable pull DOWN
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//bit2 enable ST
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//bit3 enable SlewRate Limit
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//bit4..5 Driving Strength
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//bit6..7 not used
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#define APB_SOC_BOOTADDR_OFFSET 0x04
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#define APB_SOC_INFO_OFFSET 0x00 //contains number of cores [31:16] and clusters [15:0]
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#define APB_SOC_INFOEXTD_OFFSET 0x04 //not used at the moment
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#define APB_SOC_NOTUSED0_OFFSET 0x08 //not used at the moment
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#define APB_SOC_CLUSTER_ISOLATE_OFFSET 0x0C //not used at the moment
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#define APB_SOC_PADFUN0_OFFSET 0x10
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#define APB_SOC_PADCFG0_OFFSET 0x20
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#define APB_SOC_PADFUN_OFFSET(g) (APB_SOC_PADFUN0_OFFSET+(g)*4) //sets the mux for pins g*16+0 (bits [1:0]) to g*16+15 (bits [31:30])
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#define APB_SOC_PADFUN_NO(pad) ((pad) >> 4)
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#define APB_SOC_PADFUN_PAD(padfun) ((padfun)*16)
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#define APB_SOC_PADFUN_SIZE 2
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#define ARCHI_APB_SOC_PADFUN_NB 4
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#define APB_SOC_PADFUN_BIT(pad) (((pad) & 0xF) << 1)
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#define APB_SOC_PADCFG_OFFSET(g) (APB_SOC_PADCFG0_OFFSET+(g)*4) //sets config for pin g*4+0(bits [7:0]) to pin g*4+3(bits [31:24])
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#define APB_SOC_PADCFG_NO(pad) ((pad) >> 2)
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#define APB_SOC_PADCFG_PAD(padfun) ((padfun)*4)
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#define APB_SOC_PADCFG_SIZE 8
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#define APB_SOC_PADCFG_BIT(pad) (((pad) & 0x3) << 3)
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#define APB_SOC_PWRCMD_OFFSET 0x60 //change power mode(not funtional yet)
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#define APB_SOC_PWRCFG_OFFSET 0x64 //configures power modes(not funtional yet)
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#define APB_SOC_PWRREG_OFFSET 0x68 //32 bit GP register used by power pngmt routines to see if is hard or cold reboot
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#define APB_SOC_BUSY_OFFSET 0x6C //not used at the moment
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#define APB_SOC_MMARGIN_OFFSET 0x70 //memory margin pins(not used at the moment)
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#define APB_SOC_JTAG_REG 0x74 // R/W register for interaction with the the chip environment
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#define APB_SOC_L2_SLEEP_OFFSET 0x78 //memory margin pins(not used at the moment)
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#define APB_SOC_NOTUSED3_OFFSET 0x7C //not used at the moment
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#define APB_SOC_CLKDIV0_OFFSET 0x80 //soc clock divider(to be removed)
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#define APB_SOC_CLKDIV1_OFFSET 0x84 //cluster clock divider(to be removed)
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#define APB_SOC_CLKDIV2_OFFSET 0x88 //not used at the moment
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#define APB_SOC_CLKDIV3_OFFSET 0x8C //not used at the moment
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#define APB_SOC_CLKDIV4_OFFSET 0x90 //not used at the moment
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#define APB_SOC_NOTUSED4_OFFSET 0x94 //not used at the moment
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#define APB_SOC_NOTUSED5_OFFSET 0x98 //not used at the moment
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#define APB_SOC_NOTUSED6_OFFSET 0x9C //not used at the moment
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#define APB_SOC_CORESTATUS_OFFSET 0xA0 //32bit GP register to be used during testing to return EOC(bit[31]) and status(bit[30:0])
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#define APB_SOC_CORESTATUS_RO_OFFSET 0xC0 //32bit GP register to be used during testing to return EOC(bit[31]) and status(bit[30:0])
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#define APB_SOC_PADS_CONFIG 0xC4
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#define APB_SOC_PADS_CONFIG_BOOTSEL_BIT 0
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#define APB_SOC_JTAG_REG_EXT_BIT 8
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#define APB_SOC_JTAG_REG_EXT_WIDTH 4
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#define APB_SOC_JTAG_REG_LOC_BIT 0
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#define APB_SOC_JTAG_REG_LOC_WIDTH 4
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#define APB_SOC_INFO_CORES_OFFSET (APB_SOC_INFO_OFFSET + 2)
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#define APB_SOC_INFO_CLUSTERS_OFFSET (APB_SOC_INFO_OFFSET)
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#define APB_SOC_STATUS_EOC_BIT 31
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#define APB_SOC_NB_CORE_BIT 16
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#define APB_SOC_BYPASS_OFFSET 0x70
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#define APB_SOC_BYPASS_CLOCK_GATE_BIT 10
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#define APB_SOC_BYPASS_CLUSTER_STATE_BIT 3
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#define APB_SOC_BYPASS_USER0_BIT 14
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#define APB_SOC_BYPASS_USER1_BIT 15
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#define APB_SOC_FLL_CTRL_OFFSET 0xD0
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#define APB_SOC_CLKDIV_SOC_OFFSET 0xD4
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#define APB_SOC_CLKDIV_CLUSTER_OFFSET 0xD8
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#define APB_SOC_CLKDIV_PERIPH_OFFSET 0xDC
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#define APB_SOC_FLL_CTRL_SOC_BIT 0
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#define APB_SOC_FLL_CTRL_CLUSTER_BIT 1
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#define APB_SOC_FLL_CTRL_PERIPH_BIT 2
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#define APB_SOC_RTC_OFFSET 0x1D0
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#endif
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116
include/archi/chips/pulpissimo/apb_soc_ctrl.h
Normal file
116
include/archi/chips/pulpissimo/apb_soc_ctrl.h
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@ -0,0 +1,116 @@
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/* THIS FILE HAS BEEN GENERATED, DO NOT MODIFY IT.
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*/
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/*
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* Copyright (C) 2018 ETH Zurich, University of Bologna
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* and GreenWaves Technologies
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*
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* Licensed under the Apache License, Version 2.0 (the "License");
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* you may not use this file except in compliance with the License.
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* You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS,
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* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*/
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#ifndef __INCLUDE_ARCHI_CHIPS_PULPISSIMO_APB_SOC_CTRL_H__
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#define __INCLUDE_ARCHI_CHIPS_PULPISSIMO_APB_SOC_CTRL_H__
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#ifndef LANGUAGE_ASSEMBLY
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#include <stdint.h>
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#include "archi/utils.h"
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#endif
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//
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// REGISTERS
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//
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// Value of pad bootsel
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#define APB_SOC_BOOTSEL_OFFSET 0xc4
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//
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// REGISTERS FIELDS
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//
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//
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// REGISTERS STRUCTS
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//
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#ifndef LANGUAGE_ASSEMBLY
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typedef union {
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struct {
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};
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unsigned int raw;
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} __attribute__((packed)) apb_soc_bootsel_t;
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#endif
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//
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// REGISTERS STRUCTS
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//
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#ifdef __GVSOC__
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class vp_apb_soc_bootsel : public vp::reg_32
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{
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public:
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};
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#endif
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//
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// REGISTERS GLOBAL STRUCT
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//
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#ifndef LANGUAGE_ASSEMBLY
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typedef struct {
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unsigned int bootsel ; // Value of pad bootsel
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} __attribute__((packed)) apb_soc_apb_soc_t;
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#endif
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//
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// REGISTERS ACCESS FUNCTIONS
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//
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#ifndef LANGUAGE_ASSEMBLY
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static inline uint32_t apb_soc_bootsel_get(uint32_t base) { return ARCHI_READ(base, APB_SOC_BOOTSEL_OFFSET); }
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static inline void apb_soc_bootsel_set(uint32_t base, uint32_t value) { ARCHI_WRITE(base, APB_SOC_BOOTSEL_OFFSET, value); }
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#endif
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//
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// REGISTERS FIELDS MACROS
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//
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#ifndef LANGUAGE_ASSEMBLY
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#endif
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#endif
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81
include/archi/chips/pulpissimo/memory_map.h
Normal file
81
include/archi/chips/pulpissimo/memory_map.h
Normal file
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@ -0,0 +1,81 @@
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/*
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* Copyright (C) 2018 ETH Zurich and University of Bologna
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*
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* Licensed under the Apache License, Version 2.0 (the "License");
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* you may not use this file except in compliance with the License.
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* You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS,
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* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*/
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#ifndef __ARCHI_PULPISSIMO_MEMORY_MAP_H__
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#define __ARCHI_PULPISSIMO_MEMORY_MAP_H__
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/*
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* SOC PERIPHERALS
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*/
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#define ARCHI_SOC_PERIPHERALS_ADDR 0x1A100000
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#define ARCHI_FC_TIMER_SIZE 0x00000800
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#define ARCHI_FLL_OFFSET 0x00000000
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#define ARCHI_GPIO_OFFSET 0x00001000
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#define ARCHI_UDMA_OFFSET 0x00002000
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#define ARCHI_APB_SOC_CTRL_OFFSET 0x00004000
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#define ARCHI_SOC_EU_OFFSET 0x00006000
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#define ARCHI_FC_ITC_OFFSET 0x00009800
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#define ARCHI_FC_TIMER_OFFSET 0x0000B000
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#define ARCHI_FC_HWPE_OFFSET 0x0000C000
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#define ARCHI_STDOUT_OFFSET 0x0000F000
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#define ARCHI_GPIO_ADDR ( ARCHI_SOC_PERIPHERALS_ADDR + ARCHI_GPIO_OFFSET )
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#define ARCHI_UDMA_ADDR ( ARCHI_SOC_PERIPHERALS_ADDR + ARCHI_UDMA_OFFSET )
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#define ARCHI_APB_SOC_CTRL_ADDR ( ARCHI_SOC_PERIPHERALS_ADDR + ARCHI_APB_SOC_CTRL_OFFSET )
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#define ARCHI_SOC_EU_ADDR ( ARCHI_SOC_PERIPHERALS_ADDR + ARCHI_SOC_EU_OFFSET )
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#define ARCHI_FC_ITC_ADDR ( ARCHI_SOC_PERIPHERALS_ADDR + ARCHI_FC_ITC_OFFSET )
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#define ARCHI_FC_TIMER_ADDR ( ARCHI_SOC_PERIPHERALS_ADDR + ARCHI_FC_TIMER_OFFSET )
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#define ARCHI_FC_HWPE_ADDR ( ARCHI_SOC_PERIPHERALS_ADDR + ARCHI_FC_HWPE_OFFSET )
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#define ARCHI_STDOUT_ADDR ( ARCHI_SOC_PERIPHERALS_ADDR + ARCHI_STDOUT_OFFSET )
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#define ARCHI_FLL_AREA_SIZE 0x00000010
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/*
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* CLUSTER
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*/
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#define ARCHI_CLUSTER_ADDR 0x00000000
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#define ARCHI_CLUSTER_SIZE 0x00400000
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#define ARCHI_CLUSTER_GLOBAL_ADDR(cid) (0x10000000 + (cid)*ARCHI_CLUSTER_SIZE)
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/*
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* CLUSTER PERIPHERALS
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*/
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#define ARCHI_CLUSTER_PERIPHERALS_OFFSET 0x00200000
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#define ARCHI_TIMER_OFFSET 0x00000400
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#define ARCHI_CLUSTER_PERIPHERALS_ADDR ( ARCHI_CLUSTER_ADDR + ARCHI_CLUSTER_PERIPHERALS_OFFSET )
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#define ARCHI_CLUSTER_PERIPHERALS_GLOBAL_ADDR(cid) ( ARCHI_CLUSTER_GLOBAL_ADDR(cid) + ARCHI_CLUSTER_PERIPHERALS_OFFSET )
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#endif
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239
include/archi/chips/pulpissimo/properties.h
Normal file
239
include/archi/chips/pulpissimo/properties.h
Normal file
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@ -0,0 +1,239 @@
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/*
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* Copyright (C) 2018 ETH Zurich and University of Bologna
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*
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* Licensed under the Apache License, Version 2.0 (the "License");
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* you may not use this file except in compliance with the License.
|
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* You may obtain a copy of the License at
|
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*
|
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* http://www.apache.org/licenses/LICENSE-2.0
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*
|
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* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
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* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
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*/
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#ifndef __ARCHI_PULPISSIMO_PROPERTIES_H__
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#define __ARCHI_PULPISSIMO_PROPERTIES_H__
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/*
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* FPGA
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*/
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#define ARCHI_FPGA_FREQUENCY 5000000
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/*
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* MEMORIES
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*/
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#define ARCHI_HAS_L2 1
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#define ARCHI_HAS_L2_MULTI 1
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#define ARCHI_L2_PRIV0_ADDR 0x1c000000
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#define ARCHI_L2_PRIV0_SIZE 0x00008000
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#define ARCHI_L2_PRIV1_ADDR 0x1c008000
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#define ARCHI_L2_PRIV1_SIZE 0x00008000
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#define ARCHI_L2_SHARED_ADDR 0x1c010000
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#define ARCHI_L2_SHARED_SIZE 0x00070000
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/*
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* MEMORY ALIAS
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*/
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#define ARCHI_HAS_L2_ALIAS 1
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/*
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* IP VERSIONS
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*/
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#define UDMA_VERSION 3
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#define PERIPH_VERSION 2
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#define TIMER_VERSION 2
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#define SOC_EU_VERSION 2
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#define APB_SOC_VERSION 3
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#define STDOUT_VERSION 2
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#define GPIO_VERSION 2
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#define ITC_VERSION 1
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#define FLL_VERSION 1
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#define RISCV_VERSION 4
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#define HWME_VERSION 1
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#define PADS_VERSION 2
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/*
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* CORE IDS
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*/
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#define ARCHI_FC_CID 31
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#define ARCHI_HAS_FC_ITC 1
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#define ARCHI_HAS_FC 1
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/*
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* CLOCKS
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*/
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#define ARCHI_REF_CLOCK_LOG2 15
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#define ARCHI_REF_CLOCK (1<<ARCHI_REF_CLOCK_LOG2)
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/*
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* UDMA
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*/
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#define ARCHI_UDMA_HAS_SPIM 1
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#define ARCHI_UDMA_HAS_UART 1
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#define ARCHI_UDMA_HAS_SDIO 1
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#define ARCHI_UDMA_HAS_I2C 1
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#define ARCHI_UDMA_HAS_I2S 1
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#define ARCHI_UDMA_HAS_CAM 1
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#define ARCHI_UDMA_HAS_TRACER 1
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#define ARCHI_UDMA_HAS_FILTER 1
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#define ARCHI_UDMA_NB_SPIM 1
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#define ARCHI_UDMA_NB_UART 1
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#define ARCHI_UDMA_NB_SDIO 1
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#define ARCHI_UDMA_NB_I2C 1
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#define ARCHI_UDMA_NB_I2S 1
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#define ARCHI_UDMA_NB_CAM 1
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#define ARCHI_UDMA_NB_TRACER 1
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#define ARCHI_UDMA_NB_FILTER 1
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#define ARCHI_UDMA_UART_ID(id) 0
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#define ARCHI_UDMA_SPIM_ID(id) 1
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#define ARCHI_UDMA_I2C_ID(id) (2 + (id))
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#define ARCHI_UDMA_SDIO_ID(id) (4 + (id))
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#define ARCHI_UDMA_I2S_ID(id) 5
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#define ARCHI_UDMA_CAM_ID(id) 6
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#define ARCHI_UDMA_FILTER_ID(id) (7 + (id))
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#define ARCHI_UDMA_TRACER_ID(id) 8
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#define ARCHI_UDMA_TGEN_ID(id) 9
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|
||||
#define ARCHI_NB_PERIPH 10
|
||||
|
||||
|
||||
|
||||
/*
|
||||
* FLLS
|
||||
*/
|
||||
|
||||
#define ARCHI_NB_FLL 2
|
||||
|
||||
|
||||
|
||||
/*
|
||||
* SOC EVENTS
|
||||
*/
|
||||
|
||||
#define ARCHI_SOC_EVENT_PERIPH_EVT_NB 160
|
||||
|
||||
#define ARCHI_SOC_EVENT_SW_NB (8)
|
||||
|
||||
#define ARCHI_SOC_EVENT_NB_TOTAL 256
|
||||
|
||||
#define ARCHI_SOC_EVENT_UDMA_NB_CHANNEL_EVT_LOG2 2
|
||||
#define ARCHI_SOC_EVENT_UDMA_NB_CHANNEL_EVT (1<<ARCHI_SOC_EVENT_UDMA_NB_CHANNEL_EVT_LOG2)
|
||||
#define ARCHI_SOC_EVENT_UDMA_FIRST_EVT 0
|
||||
#define ARCHI_SOC_EVENT_UDMA_NB_EVT (ARCHI_SOC_EVENT_UDMA_NB_CHANNEL_EVT * ARCHI_NB_PERIPH)
|
||||
#define ARCHI_SOC_EVENT_UDMA_NB_TGEN_EVT 6
|
||||
|
||||
#define ARCHI_SOC_EVENT_PERIPH_FIRST_EVT(x) ((x)*ARCHI_SOC_EVENT_UDMA_NB_CHANNEL_EVT)
|
||||
|
||||
#define ARCHI_SOC_EVENT_UART0_RX 0
|
||||
#define ARCHI_SOC_EVENT_UART0_TX 1
|
||||
#define ARCHI_SOC_EVENT_UART0_EOT 2
|
||||
#define ARCHI_SOC_EVENT_UART0_RX_DATA 3
|
||||
|
||||
#define ARCHI_SOC_EVENT_SPIM0_RX 4
|
||||
#define ARCHI_SOC_EVENT_SPIM0_TX 5
|
||||
#define ARCHI_SOC_EVENT_SPIM0_CMD 6
|
||||
#define ARCHI_SOC_EVENT_SPIM0_EOT 7
|
||||
|
||||
#define ARCHI_SOC_EVENT_I2C0_RX 8
|
||||
#define ARCHI_SOC_EVENT_I2C0_TX 9
|
||||
|
||||
#define ARCHI_SOC_EVENT_I2C1_RX 12
|
||||
#define ARCHI_SOC_EVENT_I2C1_TX 13
|
||||
|
||||
#define ARCHI_SOC_EVENT_SDIO0_RX 16
|
||||
#define ARCHI_SOC_EVENT_SDIO0_TX 17
|
||||
|
||||
#define ARCHI_SOC_EVENT_I2S0_RX 20
|
||||
#define ARCHI_SOC_EVENT_I2S0_TX 21
|
||||
|
||||
#define ARCHI_SOC_EVENT_CPI0_RX 24
|
||||
|
||||
#define ARCHI_SOC_EVENT_FILTER0_RX 28
|
||||
#define ARCHI_SOC_EVENT_FILTER0_TX 29
|
||||
|
||||
#define ARCHI_SOC_EVENT_CLUSTER_ON_OFF 31
|
||||
#define ARCHI_SOC_EVENT_MSP 37
|
||||
#define ARCHI_SOC_EVENT_ICU_MODE_CHANGED 37
|
||||
#define ARCHI_SOC_EVENT_ICU_OK 37
|
||||
#define ARCHI_SOC_EVENT_ICU_DELAYED 37
|
||||
#define ARCHI_SOC_EVENT_CLUSTER_CG_OK 35
|
||||
#define ARCHI_SOC_EVENT_PICL_OK 36
|
||||
#define ARCHI_SOC_EVENT_SCU_OK 37
|
||||
#define ARCHI_SOC_EVENT_PMU_FIRST_EVENT ARCHI_SOC_EVENT_CLUSTER_ON_OFF
|
||||
#define ARCHI_SOC_EVENT_PMU_NB_EVENTS 7
|
||||
|
||||
#define ARCHI_SOC_EVENT_GPIO 42
|
||||
|
||||
|
||||
#define ARCHI_SOC_EVENT_NB_I2S_CHANNELS 4
|
||||
#define ARCHI_SOC_EVENT_NB_UDMA_CHANNELS 19
|
||||
|
||||
#define ARCHI_SOC_EVENT_FCHWPE0 140
|
||||
#define ARCHI_SOC_EVENT_FCHWPE1 141
|
||||
|
||||
#define ARCHI_SOC_EVENT_SW_EVENT0 48
|
||||
#define ARCHI_SOC_EVENT_SW_EVENT1 49
|
||||
#define ARCHI_SOC_EVENT_SW_EVENT2 50
|
||||
#define ARCHI_SOC_EVENT_SW_EVENT3 51
|
||||
#define ARCHI_SOC_EVENT_SW_EVENT4 52
|
||||
#define ARCHI_SOC_EVENT_SW_EVENT5 53
|
||||
#define ARCHI_SOC_EVENT_SW_EVENT6 54
|
||||
#define ARCHI_SOC_EVENT_SW_EVENT7 55
|
||||
|
||||
#define ARCHI_SOC_EVENT_NB 8
|
||||
|
||||
#define ARCHI_SOC_EVENT_REF_CLK_RISE 56
|
||||
|
||||
|
||||
|
||||
/*
|
||||
* FC EVENTS
|
||||
*/
|
||||
|
||||
#define ARCHI_FC_EVT_FIRST_SW 0
|
||||
#define ARCHI_FC_EVT_NB_SW 8
|
||||
#define ARCHI_FC_EVT_TIMER0_LO 10
|
||||
#define ARCHI_FC_EVT_TIMER0_HI 11
|
||||
#define ARCHI_FC_EVT_CLK_REF 14
|
||||
#define ARCHI_FC_EVT_GPIO 15
|
||||
#define ARCHI_FC_EVT_RTC 16
|
||||
#define ARCHI_FC_EVT_ADV_TIMER0 17
|
||||
#define ARCHI_FC_EVT_ADV_TIMER1 18
|
||||
#define ARCHI_FC_EVT_ADV_TIMER2 19
|
||||
#define ARCHI_FC_EVT_ADV_TIMER3 20
|
||||
#define ARCHI_FC_EVT_CLUSTER_NOT_BUSY 21
|
||||
#define ARCHI_FC_EVT_CLUSTER_POK 22
|
||||
#define ARCHI_FC_EVT_CLUSTER_CG_OK 23
|
||||
#define ARCHI_FC_EVT_PICL_OK 24
|
||||
#define ARCHI_FC_EVT_SCU_OK 25
|
||||
#define ARCHI_FC_EVT_SOC_EVT 26
|
||||
#define ARCHI_FC_EVT_QUEUE_ERROR 29
|
||||
|
||||
|
||||
#endif
|
||||
39
include/archi/chips/pulpissimo/pulp.h
Normal file
39
include/archi/chips/pulpissimo/pulp.h
Normal file
|
|
@ -0,0 +1,39 @@
|
|||
/*
|
||||
* Copyright (C) 2018 ETH Zurich and University of Bologna
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the "License");
|
||||
* you may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
|
||||
|
||||
#ifndef __ARCHI_PULPISSIMO_PULP_H__
|
||||
#define __ARCHI_PULPISSIMO_PULP_H__
|
||||
|
||||
#include "archi/chips/pulpissimo/properties.h"
|
||||
#include "archi/chips/pulpissimo/apb_soc_ctrl.h"
|
||||
|
||||
//#include "archi/periph_v2.h"
|
||||
#include "archi/gpio/gpio_v3.h"
|
||||
#include "archi/riscv/priv_1_10.h"
|
||||
#include "archi/riscv/pcer_v2.h"
|
||||
|
||||
#include "archi/chips/pulpissimo/memory_map.h"
|
||||
#include "archi/chips/pulpissimo/apb_soc.h"
|
||||
|
||||
#include "archi/udma/cpi/udma_cpi_v1.h"
|
||||
#include "archi/udma/i2c/udma_i2c_v2.h"
|
||||
#include "archi/udma/i2s/udma_i2s_v2.h"
|
||||
#include "archi/udma/spim/udma_spim_v3.h"
|
||||
#include "archi/udma/uart/udma_uart_v1.h"
|
||||
#include "archi/udma/udma_v3.h"
|
||||
|
||||
#endif
|
||||
|
|
@ -25,6 +25,10 @@
|
|||
#define PULP_CHIP_STR pulpissimo
|
||||
#define PULP_CHIP_FAMILY_STR pulpissimo
|
||||
|
||||
#if __PLATFORM__ == ARCHI_PLATFORM_FPGA
|
||||
#define PERIPH_FREQUENCY 5000000
|
||||
#else
|
||||
#define PERIPH_FREQUENCY 50000000
|
||||
#endif
|
||||
|
||||
#endif
|
||||
|
|
|
|||
36
include/hal/chips/pulpissimo/pulp.h
Normal file
36
include/hal/chips/pulpissimo/pulp.h
Normal file
|
|
@ -0,0 +1,36 @@
|
|||
/*
|
||||
* Copyright (C) 2018 ETH Zurich and University of Bologna
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the "License");
|
||||
* you may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
|
||||
#ifndef __HAL_CHIPS_PULPISSIMO_PULP_H__
|
||||
#define __HAL_CHIPS_PULPISSIMO_PULP_H__
|
||||
|
||||
#include "hal/riscv/riscv_v5.h"
|
||||
#include "hal/itc/itc_v1.h"
|
||||
#include "hal/timer/timer_v2.h"
|
||||
#include "hal/soc_eu/soc_eu_v2.h"
|
||||
#include "hal/apb_soc/apb_soc_v3.h"
|
||||
#include "hal/fll/fll_v1.h"
|
||||
#include "archi/stdout/stdout_v3.h"
|
||||
#include "hal/gpio/gpio_v3.h"
|
||||
#include "hal/rom/rom_v2.h"
|
||||
|
||||
#include "hal/udma/udma_v3.h"
|
||||
#include "hal/udma/cpi/udma_cpi_v1.h"
|
||||
#include "hal/udma/i2c/udma_i2c_v2.h"
|
||||
#include "hal/udma/spim/udma_spim_v3.h"
|
||||
#include "hal/udma/uart/udma_uart_v1.h"
|
||||
|
||||
#endif
|
||||
|
|
@ -59,6 +59,8 @@ static inline void pmsis_exit(int err)
|
|||
pos_kernel_pmsis_exit_value = err;
|
||||
}
|
||||
|
||||
#ifdef ARCHI_HAS_CLUSTER
|
||||
|
||||
static inline unsigned int tas_addr(unsigned int addr)
|
||||
{
|
||||
return addr | (1<<ARCHI_L1_TAS_BIT);
|
||||
|
|
@ -79,6 +81,7 @@ static inline void tas_unlock_32(unsigned int addr, signed int value)
|
|||
__asm__ __volatile__ ("" : : : "memory");
|
||||
}
|
||||
|
||||
#endif
|
||||
|
||||
#include "alloc.h"
|
||||
#include "irq.h"
|
||||
|
|
|
|||
|
|
@ -63,8 +63,6 @@ static inline void pos_irq_mask_clr(unsigned int mask)
|
|||
#if defined(__RISCV_GENERIC__)
|
||||
hal_spr_read_then_clr_from_reg(0x304, mask);
|
||||
|
||||
#error 1
|
||||
|
||||
#elif defined(ITC_VERSION) && defined(EU_VERSION)
|
||||
if (hal_is_fc())
|
||||
hal_itc_enable_clr(mask);
|
||||
|
|
@ -72,12 +70,10 @@ static inline void pos_irq_mask_clr(unsigned int mask)
|
|||
eu_irq_maskClr(mask);
|
||||
|
||||
#elif defined(ITC_VERSION)
|
||||
#error 2
|
||||
|
||||
hal_itc_enable_clr(mask);
|
||||
|
||||
#elif defined(EU_VERSION)
|
||||
#error 3
|
||||
eu_irq_maskClr(mask);
|
||||
if (hal_is_fc())
|
||||
eu_evt_maskClr(mask);
|
||||
|
|
|
|||
|
|
@ -143,10 +143,12 @@ pos_semihosting_call:
|
|||
|
||||
|
||||
|
||||
#if defined(ARCHI_HAS_CLUSTER)
|
||||
pe_start:
|
||||
la x2, cluster_stacks
|
||||
li x3, CLUSTER_STACK_SIZE
|
||||
addi a1, a1, 1
|
||||
mul x1, x3, a1
|
||||
add x2, x2, x1
|
||||
j cluster_entry_stub
|
||||
j cluster_entry_stub
|
||||
#endif
|
||||
|
|
@ -33,10 +33,6 @@ platform=$(PULPRUN_PLATFORM)
|
|||
endif
|
||||
|
||||
|
||||
ifndef platform
|
||||
platform=gvsoc
|
||||
endif
|
||||
|
||||
override disopt ?= -d
|
||||
|
||||
ifeq '$(platform)' 'gvsoc'
|
||||
|
|
|
|||
|
|
@ -6,7 +6,11 @@ ifeq '$(CONFIG_LIBC_MINIMAL)' '1'
|
|||
PULP_SRCS += lib/libc/minimal/io.c lib/libc/minimal/fprintf.c lib/libc/minimal/prf.c lib/libc/minimal/sprintf.c
|
||||
endif
|
||||
|
||||
PULP_SRCS += kernel/init.c kernel/kernel.c kernel/alloc.c kernel/alloc_pool.c kernel/irq.c kernel/soc_event.c kernel/bench.c kernel/cluster.c drivers/uart.c
|
||||
PULP_SRCS += kernel/init.c kernel/kernel.c kernel/alloc.c kernel/alloc_pool.c kernel/irq.c kernel/soc_event.c kernel/bench.c drivers/uart.c
|
||||
|
||||
PULP_ASM_SRCS += kernel/irq_asm.S
|
||||
|
||||
|
||||
ifneq '$(cluster/version)' ''
|
||||
PULP_SRCS += kernel/cluster.c
|
||||
endif
|
||||
|
|
@ -3,7 +3,7 @@ PULP_CFLAGS += -D__riscv__
|
|||
PULP_ARCH_CFLAGS ?= -march=rv32imcxgap9
|
||||
PULP_ARCH_LDFLAGS ?= -march=rv32imcxgap9
|
||||
PULP_ARCH_OBJDFLAGS ?= -Mmarch=rv32imcxgap9
|
||||
PULP_CFLAGS += -fdata-sections -ffunction-sections -include chips/pulp/config.h -I$(PULPRT_HOME)/include/chips/pulpissimo
|
||||
PULP_CFLAGS += -fdata-sections -ffunction-sections -include chips/pulpissimo/config.h -I$(PULPRT_HOME)/include/chips/pulpissimo
|
||||
PULP_OMP_CFLAGS += -fopenmp -mnativeomp
|
||||
PULP_LDFLAGS += -nostartfiles -nostdlib -Wl,--gc-sections -L$(PULPRT_HOME)/kernel -Tchips/pulpissimo/link.ld -lgcc
|
||||
|
||||
|
|
@ -16,7 +16,6 @@ fc/archi=riscv
|
|||
pe/archi=riscv
|
||||
pulp_chip=pulp
|
||||
pulp_chip_family=pulp
|
||||
cluster/version=5
|
||||
fc_itc/version=1
|
||||
udma/cpi/version=1
|
||||
udma/i2c/version=2
|
||||
|
|
|
|||
Loading…
Reference in a new issue