diff --git a/include/archi/chips/pulpissimo/apb_soc.h b/include/archi/chips/pulpissimo/apb_soc.h
new file mode 100644
index 0000000..c403f13
--- /dev/null
+++ b/include/archi/chips/pulpissimo/apb_soc.h
@@ -0,0 +1,121 @@
+/*
+ * Copyright (C) 2018 ETH Zurich and University of Bologna
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __ARCHI_PULPISSIMO_APB_SOC_H__
+#define __ARCHI_PULPISSIMO_APB_SOC_H__
+ 
+#define APB_SOC_BOOT_OTHER    0
+#define APB_SOC_BOOT_JTAG     1
+#define APB_SOC_BOOT_SPI      2
+#define APB_SOC_BOOT_ROM      3
+#define APB_SOC_BOOT_PRELOAD  4
+#define APB_SOC_BOOT_HYPER    5
+#define APB_SOC_BOOT_SPIM     6
+#define APB_SOC_BOOT_SPIM_QPI 7
+
+#define APB_SOC_PLT_OTHER   0
+#define APB_SOC_PLT_FPGA    1
+#define APB_SOC_PLT_RTL     2
+#define APB_SOC_PLT_VP      3
+#define APB_SOC_PLT_CHIP    4
+ 
+//PADs configuration is made of 8bits out of which only the first 6 are used
+//bit0    enable pull UP
+//bit1    enable pull DOWN
+//bit2    enable ST
+//bit3    enable SlewRate Limit
+//bit4..5 Driving Strength
+//bit6..7 not used
+
+#define APB_SOC_BOOTADDR_OFFSET   0x04
+#define APB_SOC_INFO_OFFSET       0x00 //contains number of cores [31:16] and clusters [15:0]
+#define APB_SOC_INFOEXTD_OFFSET   0x04 //not used at the moment
+#define APB_SOC_NOTUSED0_OFFSET   0x08 //not used at the moment
+#define APB_SOC_CLUSTER_ISOLATE_OFFSET   0x0C //not used at the moment
+
+#define	APB_SOC_PADFUN0_OFFSET	  0x10
+#define	APB_SOC_PADCFG0_OFFSET	  0x20
+
+#define APB_SOC_PADFUN_OFFSET(g)   (APB_SOC_PADFUN0_OFFSET+(g)*4) //sets the mux for pins  g*16+0 (bits [1:0]) to g*16+15 (bits [31:30])
+#define APB_SOC_PADFUN_NO(pad)     ((pad) >> 4)
+#define APB_SOC_PADFUN_PAD(padfun) ((padfun)*16)
+#define APB_SOC_PADFUN_SIZE        2
+#define ARCHI_APB_SOC_PADFUN_NB          4
+#define APB_SOC_PADFUN_BIT(pad)    (((pad) & 0xF) << 1)
+
+#define APB_SOC_PADCFG_OFFSET(g)   (APB_SOC_PADCFG0_OFFSET+(g)*4) //sets config for pin  g*4+0(bits [7:0]) to pin  g*4+3(bits [31:24])
+#define APB_SOC_PADCFG_NO(pad)     ((pad) >> 2)
+#define APB_SOC_PADCFG_PAD(padfun) ((padfun)*4)
+#define APB_SOC_PADCFG_SIZE        8
+#define APB_SOC_PADCFG_BIT(pad)    (((pad) & 0x3) << 3)
+ 
+#define APB_SOC_PWRCMD_OFFSET     0x60 //change power mode(not funtional yet)
+#define APB_SOC_PWRCFG_OFFSET     0x64 //configures power modes(not funtional yet)
+#define APB_SOC_PWRREG_OFFSET     0x68 //32 bit GP register used by power pngmt routines to see if is hard or cold reboot
+#define APB_SOC_BUSY_OFFSET       0x6C //not used at the moment
+#define APB_SOC_MMARGIN_OFFSET    0x70 //memory margin pins(not used at the moment)
+#define APB_SOC_JTAG_REG          0x74 // R/W register for interaction with the the chip environment
+#define APB_SOC_L2_SLEEP_OFFSET   0x78 //memory margin pins(not used at the moment)
+#define APB_SOC_NOTUSED3_OFFSET   0x7C //not used at the moment
+#define APB_SOC_CLKDIV0_OFFSET    0x80 //soc clock divider(to be removed)
+#define APB_SOC_CLKDIV1_OFFSET    0x84 //cluster clock divider(to be removed)
+#define APB_SOC_CLKDIV2_OFFSET    0x88 //not used at the moment
+#define APB_SOC_CLKDIV3_OFFSET    0x8C //not used at the moment
+#define APB_SOC_CLKDIV4_OFFSET    0x90 //not used at the moment
+#define APB_SOC_NOTUSED4_OFFSET   0x94 //not used at the moment
+#define APB_SOC_NOTUSED5_OFFSET   0x98 //not used at the moment
+#define APB_SOC_NOTUSED6_OFFSET   0x9C //not used at the moment
+#define APB_SOC_CORESTATUS_OFFSET 0xA0 //32bit GP register to be used during testing to return EOC(bit[31]) and status(bit[30:0])
+#define APB_SOC_CORESTATUS_RO_OFFSET 0xC0 //32bit GP register to be used during testing to return EOC(bit[31]) and status(bit[30:0])
+#define APB_SOC_PADS_CONFIG       0xC4
+
+#define APB_SOC_PADS_CONFIG_BOOTSEL_BIT 0
+
+#define APB_SOC_JTAG_REG_EXT_BIT   8
+#define APB_SOC_JTAG_REG_EXT_WIDTH 4
+
+#define APB_SOC_JTAG_REG_LOC_BIT   0
+#define APB_SOC_JTAG_REG_LOC_WIDTH 4
+
+#define APB_SOC_INFO_CORES_OFFSET    (APB_SOC_INFO_OFFSET + 2)
+#define APB_SOC_INFO_CLUSTERS_OFFSET (APB_SOC_INFO_OFFSET)
+
+#define APB_SOC_STATUS_EOC_BIT  31
+#define APB_SOC_NB_CORE_BIT     16
+
+
+#define APB_SOC_BYPASS_OFFSET   0x70
+
+#define APB_SOC_BYPASS_CLOCK_GATE_BIT 10
+#define APB_SOC_BYPASS_CLUSTER_STATE_BIT 3
+#define APB_SOC_BYPASS_USER0_BIT       14
+#define APB_SOC_BYPASS_USER1_BIT       15
+
+
+#define APB_SOC_FLL_CTRL_OFFSET         0xD0
+#define APB_SOC_CLKDIV_SOC_OFFSET       0xD4
+#define APB_SOC_CLKDIV_CLUSTER_OFFSET   0xD8
+#define APB_SOC_CLKDIV_PERIPH_OFFSET    0xDC
+
+
+#define APB_SOC_FLL_CTRL_SOC_BIT        0
+#define APB_SOC_FLL_CTRL_CLUSTER_BIT    1
+#define APB_SOC_FLL_CTRL_PERIPH_BIT     2
+
+
+#define APB_SOC_RTC_OFFSET     0x1D0
+
+#endif
diff --git a/include/archi/chips/pulpissimo/apb_soc_ctrl.h b/include/archi/chips/pulpissimo/apb_soc_ctrl.h
new file mode 100644
index 0000000..f364de1
--- /dev/null
+++ b/include/archi/chips/pulpissimo/apb_soc_ctrl.h
@@ -0,0 +1,116 @@
+
+/* THIS FILE HAS BEEN GENERATED, DO NOT MODIFY IT.
+ */
+
+/*
+ * Copyright (C) 2018 ETH Zurich, University of Bologna
+ * and GreenWaves Technologies
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __INCLUDE_ARCHI_CHIPS_PULPISSIMO_APB_SOC_CTRL_H__
+#define __INCLUDE_ARCHI_CHIPS_PULPISSIMO_APB_SOC_CTRL_H__
+
+#ifndef LANGUAGE_ASSEMBLY
+
+#include <stdint.h>
+#include "archi/utils.h"
+
+#endif
+
+
+
+
+//
+// REGISTERS
+//
+
+// Value of pad bootsel
+#define APB_SOC_BOOTSEL_OFFSET                   0xc4
+
+
+
+//
+// REGISTERS FIELDS
+//
+
+
+
+//
+// REGISTERS STRUCTS
+//
+
+#ifndef LANGUAGE_ASSEMBLY
+
+typedef union {
+  struct {
+  };
+  unsigned int raw;
+} __attribute__((packed)) apb_soc_bootsel_t;
+
+#endif
+
+
+
+//
+// REGISTERS STRUCTS
+//
+
+#ifdef __GVSOC__
+
+class vp_apb_soc_bootsel : public vp::reg_32
+{
+public:
+};
+
+#endif
+
+
+
+//
+// REGISTERS GLOBAL STRUCT
+//
+
+#ifndef LANGUAGE_ASSEMBLY
+
+typedef struct {
+  unsigned int bootsel         ; // Value of pad bootsel
+} __attribute__((packed)) apb_soc_apb_soc_t;
+
+#endif
+
+
+
+//
+// REGISTERS ACCESS FUNCTIONS
+//
+
+#ifndef LANGUAGE_ASSEMBLY
+
+static inline uint32_t apb_soc_bootsel_get(uint32_t base) { return ARCHI_READ(base, APB_SOC_BOOTSEL_OFFSET); }
+static inline void apb_soc_bootsel_set(uint32_t base, uint32_t value) { ARCHI_WRITE(base, APB_SOC_BOOTSEL_OFFSET, value); }
+
+#endif
+
+
+
+//
+// REGISTERS FIELDS MACROS
+//
+
+#ifndef LANGUAGE_ASSEMBLY
+
+#endif
+
+#endif
diff --git a/include/archi/chips/pulpissimo/memory_map.h b/include/archi/chips/pulpissimo/memory_map.h
new file mode 100644
index 0000000..4e226bb
--- /dev/null
+++ b/include/archi/chips/pulpissimo/memory_map.h
@@ -0,0 +1,81 @@
+/*
+ * Copyright (C) 2018 ETH Zurich and University of Bologna
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+
+#ifndef __ARCHI_PULPISSIMO_MEMORY_MAP_H__
+#define __ARCHI_PULPISSIMO_MEMORY_MAP_H__
+
+
+
+/*
+ * SOC PERIPHERALS
+ */
+
+#define ARCHI_SOC_PERIPHERALS_ADDR    0x1A100000
+
+#define ARCHI_FC_TIMER_SIZE                 0x00000800
+
+#define ARCHI_FLL_OFFSET              0x00000000
+#define ARCHI_GPIO_OFFSET             0x00001000
+#define ARCHI_UDMA_OFFSET             0x00002000
+#define ARCHI_APB_SOC_CTRL_OFFSET     0x00004000
+#define ARCHI_SOC_EU_OFFSET           0x00006000
+#define ARCHI_FC_ITC_OFFSET           0x00009800
+#define ARCHI_FC_TIMER_OFFSET         0x0000B000
+#define ARCHI_FC_HWPE_OFFSET          0x0000C000
+#define ARCHI_STDOUT_OFFSET           0x0000F000
+
+
+
+#define ARCHI_GPIO_ADDR              ( ARCHI_SOC_PERIPHERALS_ADDR + ARCHI_GPIO_OFFSET )
+#define ARCHI_UDMA_ADDR              ( ARCHI_SOC_PERIPHERALS_ADDR + ARCHI_UDMA_OFFSET )
+#define ARCHI_APB_SOC_CTRL_ADDR      ( ARCHI_SOC_PERIPHERALS_ADDR + ARCHI_APB_SOC_CTRL_OFFSET )
+#define ARCHI_SOC_EU_ADDR            ( ARCHI_SOC_PERIPHERALS_ADDR + ARCHI_SOC_EU_OFFSET )
+#define ARCHI_FC_ITC_ADDR            ( ARCHI_SOC_PERIPHERALS_ADDR + ARCHI_FC_ITC_OFFSET )
+#define ARCHI_FC_TIMER_ADDR          ( ARCHI_SOC_PERIPHERALS_ADDR + ARCHI_FC_TIMER_OFFSET )
+#define ARCHI_FC_HWPE_ADDR           ( ARCHI_SOC_PERIPHERALS_ADDR + ARCHI_FC_HWPE_OFFSET )
+#define ARCHI_STDOUT_ADDR            ( ARCHI_SOC_PERIPHERALS_ADDR + ARCHI_STDOUT_OFFSET )
+
+
+
+#define ARCHI_FLL_AREA_SIZE          0x00000010
+
+
+
+
+/*
+ * CLUSTER
+ */
+
+#define ARCHI_CLUSTER_ADDR              0x00000000
+#define ARCHI_CLUSTER_SIZE              0x00400000
+#define ARCHI_CLUSTER_GLOBAL_ADDR(cid)  (0x10000000 + (cid)*ARCHI_CLUSTER_SIZE)
+
+
+
+/*
+ * CLUSTER PERIPHERALS
+ */
+
+#define ARCHI_CLUSTER_PERIPHERALS_OFFSET 0x00200000
+
+#define ARCHI_TIMER_OFFSET               0x00000400
+
+#define ARCHI_CLUSTER_PERIPHERALS_ADDR             ( ARCHI_CLUSTER_ADDR + ARCHI_CLUSTER_PERIPHERALS_OFFSET )
+#define ARCHI_CLUSTER_PERIPHERALS_GLOBAL_ADDR(cid) ( ARCHI_CLUSTER_GLOBAL_ADDR(cid) + ARCHI_CLUSTER_PERIPHERALS_OFFSET )
+
+
+#endif
diff --git a/include/archi/chips/pulpissimo/properties.h b/include/archi/chips/pulpissimo/properties.h
new file mode 100644
index 0000000..7a7f126
--- /dev/null
+++ b/include/archi/chips/pulpissimo/properties.h
@@ -0,0 +1,239 @@
+/*
+ * Copyright (C) 2018 ETH Zurich and University of Bologna
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+
+#ifndef __ARCHI_PULPISSIMO_PROPERTIES_H__
+#define __ARCHI_PULPISSIMO_PROPERTIES_H__
+
+/*
+ * FPGA
+ */
+
+#define ARCHI_FPGA_FREQUENCY 5000000
+
+
+/*
+ * MEMORIES
+ */ 
+
+#define ARCHI_HAS_L2                   1
+#define ARCHI_HAS_L2_MULTI             1
+
+#define ARCHI_L2_PRIV0_ADDR  0x1c000000
+#define ARCHI_L2_PRIV0_SIZE  0x00008000
+
+#define ARCHI_L2_PRIV1_ADDR  0x1c008000
+#define ARCHI_L2_PRIV1_SIZE  0x00008000
+
+#define ARCHI_L2_SHARED_ADDR  0x1c010000
+#define ARCHI_L2_SHARED_SIZE  0x00070000
+
+
+
+/*
+ * MEMORY ALIAS
+ */
+
+#define ARCHI_HAS_L2_ALIAS             1
+
+
+
+/*
+ * IP VERSIONS
+ */
+
+#define UDMA_VERSION        3
+#define PERIPH_VERSION      2
+#define TIMER_VERSION       2
+#define SOC_EU_VERSION      2
+#define APB_SOC_VERSION     3
+#define STDOUT_VERSION      2
+#define GPIO_VERSION        2
+#define ITC_VERSION         1
+#define FLL_VERSION         1
+#define RISCV_VERSION       4
+#define HWME_VERSION        1
+#define PADS_VERSION        2
+
+
+/*
+ * CORE IDS
+ */
+
+#define ARCHI_FC_CID        31
+#define ARCHI_HAS_FC_ITC     1
+#define ARCHI_HAS_FC         1
+
+
+
+/*
+ * CLOCKS
+ */
+
+#define ARCHI_REF_CLOCK_LOG2 15
+#define ARCHI_REF_CLOCK      (1<<ARCHI_REF_CLOCK_LOG2)
+
+
+
+/*
+ * UDMA
+ */
+
+#define ARCHI_UDMA_HAS_SPIM   1
+#define ARCHI_UDMA_HAS_UART   1
+#define ARCHI_UDMA_HAS_SDIO      1
+#define ARCHI_UDMA_HAS_I2C    1
+#define ARCHI_UDMA_HAS_I2S    1
+#define ARCHI_UDMA_HAS_CAM    1
+#define ARCHI_UDMA_HAS_TRACER 1
+#define ARCHI_UDMA_HAS_FILTER    1
+
+#define ARCHI_UDMA_NB_SPIM   1
+#define ARCHI_UDMA_NB_UART   1
+#define ARCHI_UDMA_NB_SDIO      1
+#define ARCHI_UDMA_NB_I2C    1
+#define ARCHI_UDMA_NB_I2S    1
+#define ARCHI_UDMA_NB_CAM    1
+#define ARCHI_UDMA_NB_TRACER 1
+#define ARCHI_UDMA_NB_FILTER    1
+
+#define ARCHI_UDMA_UART_ID(id)            0
+#define ARCHI_UDMA_SPIM_ID(id)            1
+#define ARCHI_UDMA_I2C_ID(id)             (2 + (id))
+#define ARCHI_UDMA_SDIO_ID(id)            (4   + (id))
+#define ARCHI_UDMA_I2S_ID(id)             5
+#define ARCHI_UDMA_CAM_ID(id)             6
+#define ARCHI_UDMA_FILTER_ID(id)          (7  + (id))
+#define ARCHI_UDMA_TRACER_ID(id)          8
+#define ARCHI_UDMA_TGEN_ID(id)            9
+
+#define ARCHI_NB_PERIPH                   10
+
+
+
+/*
+ * FLLS
+*/
+
+#define ARCHI_NB_FLL  2
+
+
+
+/*
+ * SOC EVENTS
+ */
+
+#define ARCHI_SOC_EVENT_PERIPH_EVT_NB     160
+
+#define ARCHI_SOC_EVENT_SW_NB      (8)
+
+#define ARCHI_SOC_EVENT_NB_TOTAL     256
+
+#define ARCHI_SOC_EVENT_UDMA_NB_CHANNEL_EVT_LOG2 2
+#define ARCHI_SOC_EVENT_UDMA_NB_CHANNEL_EVT (1<<ARCHI_SOC_EVENT_UDMA_NB_CHANNEL_EVT_LOG2)
+#define ARCHI_SOC_EVENT_UDMA_FIRST_EVT   0
+#define ARCHI_SOC_EVENT_UDMA_NB_EVT       (ARCHI_SOC_EVENT_UDMA_NB_CHANNEL_EVT * ARCHI_NB_PERIPH)
+#define ARCHI_SOC_EVENT_UDMA_NB_TGEN_EVT 6
+
+#define ARCHI_SOC_EVENT_PERIPH_FIRST_EVT(x)     ((x)*ARCHI_SOC_EVENT_UDMA_NB_CHANNEL_EVT)
+
+#define ARCHI_SOC_EVENT_UART0_RX          0
+#define ARCHI_SOC_EVENT_UART0_TX          1
+#define ARCHI_SOC_EVENT_UART0_EOT         2
+#define ARCHI_SOC_EVENT_UART0_RX_DATA     3
+
+#define ARCHI_SOC_EVENT_SPIM0_RX          4
+#define ARCHI_SOC_EVENT_SPIM0_TX          5
+#define ARCHI_SOC_EVENT_SPIM0_CMD         6
+#define ARCHI_SOC_EVENT_SPIM0_EOT         7
+
+#define ARCHI_SOC_EVENT_I2C0_RX           8
+#define ARCHI_SOC_EVENT_I2C0_TX           9
+
+#define ARCHI_SOC_EVENT_I2C1_RX           12
+#define ARCHI_SOC_EVENT_I2C1_TX           13
+
+#define ARCHI_SOC_EVENT_SDIO0_RX          16
+#define ARCHI_SOC_EVENT_SDIO0_TX          17
+
+#define ARCHI_SOC_EVENT_I2S0_RX           20
+#define ARCHI_SOC_EVENT_I2S0_TX           21
+
+#define ARCHI_SOC_EVENT_CPI0_RX           24
+
+#define ARCHI_SOC_EVENT_FILTER0_RX        28
+#define ARCHI_SOC_EVENT_FILTER0_TX        29
+
+#define ARCHI_SOC_EVENT_CLUSTER_ON_OFF   31
+#define ARCHI_SOC_EVENT_MSP              37
+#define ARCHI_SOC_EVENT_ICU_MODE_CHANGED 37
+#define ARCHI_SOC_EVENT_ICU_OK           37
+#define ARCHI_SOC_EVENT_ICU_DELAYED      37
+#define ARCHI_SOC_EVENT_CLUSTER_CG_OK    35
+#define ARCHI_SOC_EVENT_PICL_OK          36
+#define ARCHI_SOC_EVENT_SCU_OK           37
+#define ARCHI_SOC_EVENT_PMU_FIRST_EVENT  ARCHI_SOC_EVENT_CLUSTER_ON_OFF
+#define ARCHI_SOC_EVENT_PMU_NB_EVENTS    7
+
+#define ARCHI_SOC_EVENT_GPIO         42
+
+
+#define ARCHI_SOC_EVENT_NB_I2S_CHANNELS  4
+#define ARCHI_SOC_EVENT_NB_UDMA_CHANNELS 19
+
+#define ARCHI_SOC_EVENT_FCHWPE0 140
+#define ARCHI_SOC_EVENT_FCHWPE1 141
+
+#define ARCHI_SOC_EVENT_SW_EVENT0    48
+#define ARCHI_SOC_EVENT_SW_EVENT1    49
+#define ARCHI_SOC_EVENT_SW_EVENT2    50
+#define ARCHI_SOC_EVENT_SW_EVENT3    51
+#define ARCHI_SOC_EVENT_SW_EVENT4    52
+#define ARCHI_SOC_EVENT_SW_EVENT5    53
+#define ARCHI_SOC_EVENT_SW_EVENT6    54
+#define ARCHI_SOC_EVENT_SW_EVENT7    55
+
+#define ARCHI_SOC_EVENT_NB           8
+
+#define ARCHI_SOC_EVENT_REF_CLK_RISE 56
+
+
+
+/*
+ * FC EVENTS
+ */
+
+#define ARCHI_FC_EVT_FIRST_SW         0
+#define ARCHI_FC_EVT_NB_SW            8
+#define ARCHI_FC_EVT_TIMER0_LO           10
+#define ARCHI_FC_EVT_TIMER0_HI           11
+#define ARCHI_FC_EVT_CLK_REF          14
+#define ARCHI_FC_EVT_GPIO             15
+#define ARCHI_FC_EVT_RTC              16
+#define ARCHI_FC_EVT_ADV_TIMER0       17
+#define ARCHI_FC_EVT_ADV_TIMER1       18
+#define ARCHI_FC_EVT_ADV_TIMER2       19
+#define ARCHI_FC_EVT_ADV_TIMER3       20
+#define ARCHI_FC_EVT_CLUSTER_NOT_BUSY 21
+#define ARCHI_FC_EVT_CLUSTER_POK      22
+#define ARCHI_FC_EVT_CLUSTER_CG_OK    23
+#define ARCHI_FC_EVT_PICL_OK          24
+#define ARCHI_FC_EVT_SCU_OK           25
+#define ARCHI_FC_EVT_SOC_EVT          26
+#define ARCHI_FC_EVT_QUEUE_ERROR      29
+
+
+#endif
diff --git a/include/archi/chips/pulpissimo/pulp.h b/include/archi/chips/pulpissimo/pulp.h
new file mode 100644
index 0000000..d94bf2b
--- /dev/null
+++ b/include/archi/chips/pulpissimo/pulp.h
@@ -0,0 +1,39 @@
+/*
+ * Copyright (C) 2018 ETH Zurich and University of Bologna
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+
+#ifndef __ARCHI_PULPISSIMO_PULP_H__
+#define __ARCHI_PULPISSIMO_PULP_H__
+
+#include "archi/chips/pulpissimo/properties.h"
+#include "archi/chips/pulpissimo/apb_soc_ctrl.h"
+
+//#include "archi/periph_v2.h"
+#include "archi/gpio/gpio_v3.h"
+#include "archi/riscv/priv_1_10.h"
+#include "archi/riscv/pcer_v2.h"
+
+#include "archi/chips/pulpissimo/memory_map.h"
+#include "archi/chips/pulpissimo/apb_soc.h"
+
+#include "archi/udma/cpi/udma_cpi_v1.h"
+#include "archi/udma/i2c/udma_i2c_v2.h"
+#include "archi/udma/i2s/udma_i2s_v2.h"
+#include "archi/udma/spim/udma_spim_v3.h"
+#include "archi/udma/uart/udma_uart_v1.h"
+#include "archi/udma/udma_v3.h"
+
+#endif
\ No newline at end of file
diff --git a/include/chips/pulpissimo/config.h b/include/chips/pulpissimo/config.h
index 176cb4a..dc358be 100644
--- a/include/chips/pulpissimo/config.h
+++ b/include/chips/pulpissimo/config.h
@@ -25,6 +25,10 @@
 #define PULP_CHIP_STR pulpissimo
 #define PULP_CHIP_FAMILY_STR pulpissimo
 
+#if __PLATFORM__ == ARCHI_PLATFORM_FPGA
+#define PERIPH_FREQUENCY 5000000
+#else
 #define PERIPH_FREQUENCY 50000000
+#endif
 
 #endif
diff --git a/include/hal/chips/pulpissimo/pulp.h b/include/hal/chips/pulpissimo/pulp.h
new file mode 100644
index 0000000..8d10be9
--- /dev/null
+++ b/include/hal/chips/pulpissimo/pulp.h
@@ -0,0 +1,36 @@
+/*
+ * Copyright (C) 2018 ETH Zurich and University of Bologna
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __HAL_CHIPS_PULPISSIMO_PULP_H__
+#define __HAL_CHIPS_PULPISSIMO_PULP_H__
+
+#include "hal/riscv/riscv_v5.h"
+#include "hal/itc/itc_v1.h"
+#include "hal/timer/timer_v2.h"
+#include "hal/soc_eu/soc_eu_v2.h"
+#include "hal/apb_soc/apb_soc_v3.h"
+#include "hal/fll/fll_v1.h"
+#include "archi/stdout/stdout_v3.h"
+#include "hal/gpio/gpio_v3.h"
+#include "hal/rom/rom_v2.h"
+
+#include "hal/udma/udma_v3.h"
+#include "hal/udma/cpi/udma_cpi_v1.h"
+#include "hal/udma/i2c/udma_i2c_v2.h"
+#include "hal/udma/spim/udma_spim_v3.h"
+#include "hal/udma/uart/udma_uart_v1.h"
+
+#endif
\ No newline at end of file
diff --git a/include/implem/implem.h b/include/implem/implem.h
index 9fa564d..cac1d61 100644
--- a/include/implem/implem.h
+++ b/include/implem/implem.h
@@ -59,6 +59,8 @@ static inline void pmsis_exit(int err)
     pos_kernel_pmsis_exit_value = err;
 }
 
+#ifdef ARCHI_HAS_CLUSTER
+
 static inline unsigned int tas_addr(unsigned int addr)
 {
   return addr | (1<<ARCHI_L1_TAS_BIT);
@@ -79,6 +81,7 @@ static inline void tas_unlock_32(unsigned int addr, signed int value)
   __asm__ __volatile__ ("" : : : "memory");
 }
 
+#endif
 
 #include "alloc.h"
 #include "irq.h"
diff --git a/include/implem/irq.h b/include/implem/irq.h
index 9dc0dd2..326dfe9 100644
--- a/include/implem/irq.h
+++ b/include/implem/irq.h
@@ -63,8 +63,6 @@ static inline void pos_irq_mask_clr(unsigned int mask)
 #if defined(__RISCV_GENERIC__)
     hal_spr_read_then_clr_from_reg(0x304, mask);
 
-    #error 1
-
 #elif defined(ITC_VERSION) && defined(EU_VERSION)
     if (hal_is_fc())
         hal_itc_enable_clr(mask);
@@ -72,12 +70,10 @@ static inline void pos_irq_mask_clr(unsigned int mask)
         eu_irq_maskClr(mask);
 
 #elif defined(ITC_VERSION)
-    #error 2
 
     hal_itc_enable_clr(mask);
 
 #elif defined(EU_VERSION)
-    #error 3
     eu_irq_maskClr(mask);
     if (hal_is_fc())
         eu_evt_maskClr(mask);
diff --git a/kernel/crt0.S b/kernel/crt0.S
index 3d24c3e..9f5504a 100644
--- a/kernel/crt0.S
+++ b/kernel/crt0.S
@@ -143,10 +143,12 @@ pos_semihosting_call:
 
 
 
+#if defined(ARCHI_HAS_CLUSTER)
 pe_start:
     la   x2, cluster_stacks
     li   x3, CLUSTER_STACK_SIZE
     addi a1, a1, 1
     mul  x1, x3, a1
     add  x2, x2, x1
-    j    cluster_entry_stub
\ No newline at end of file
+    j    cluster_entry_stub
+#endif
\ No newline at end of file
diff --git a/rules/pulpos/default_rules.mk b/rules/pulpos/default_rules.mk
index a6801b1..63dcd3d 100644
--- a/rules/pulpos/default_rules.mk
+++ b/rules/pulpos/default_rules.mk
@@ -33,10 +33,6 @@ platform=$(PULPRUN_PLATFORM)
 endif
 
 
-ifndef platform
-platform=gvsoc
-endif
-
 override disopt ?= -d
 
 ifeq '$(platform)' 'gvsoc'
diff --git a/rules/pulpos/src.mk b/rules/pulpos/src.mk
index 3742191..e7b065e 100644
--- a/rules/pulpos/src.mk
+++ b/rules/pulpos/src.mk
@@ -6,7 +6,11 @@ ifeq '$(CONFIG_LIBC_MINIMAL)' '1'
 PULP_SRCS += lib/libc/minimal/io.c lib/libc/minimal/fprintf.c lib/libc/minimal/prf.c lib/libc/minimal/sprintf.c
 endif
 
-PULP_SRCS += kernel/init.c kernel/kernel.c kernel/alloc.c kernel/alloc_pool.c kernel/irq.c kernel/soc_event.c kernel/bench.c kernel/cluster.c drivers/uart.c
+PULP_SRCS += kernel/init.c kernel/kernel.c kernel/alloc.c kernel/alloc_pool.c kernel/irq.c kernel/soc_event.c kernel/bench.c drivers/uart.c
 
 PULP_ASM_SRCS += kernel/irq_asm.S
 
+
+ifneq '$(cluster/version)' ''
+PULP_SRCS += kernel/cluster.c
+endif
\ No newline at end of file
diff --git a/rules/pulpos/targets/pulpissimo.mk b/rules/pulpos/targets/pulpissimo.mk
index 11fb450..ba12247 100644
--- a/rules/pulpos/targets/pulpissimo.mk
+++ b/rules/pulpos/targets/pulpissimo.mk
@@ -3,7 +3,7 @@ PULP_CFLAGS       +=  -D__riscv__
 PULP_ARCH_CFLAGS ?=  -march=rv32imcxgap9
 PULP_ARCH_LDFLAGS ?=  -march=rv32imcxgap9
 PULP_ARCH_OBJDFLAGS ?= -Mmarch=rv32imcxgap9
-PULP_CFLAGS    += -fdata-sections -ffunction-sections -include chips/pulp/config.h -I$(PULPRT_HOME)/include/chips/pulpissimo
+PULP_CFLAGS    += -fdata-sections -ffunction-sections -include chips/pulpissimo/config.h -I$(PULPRT_HOME)/include/chips/pulpissimo
 PULP_OMP_CFLAGS    += -fopenmp -mnativeomp
 PULP_LDFLAGS += -nostartfiles -nostdlib -Wl,--gc-sections -L$(PULPRT_HOME)/kernel -Tchips/pulpissimo/link.ld -lgcc
 
@@ -16,7 +16,6 @@ fc/archi=riscv
 pe/archi=riscv
 pulp_chip=pulp
 pulp_chip_family=pulp
-cluster/version=5
 fc_itc/version=1
 udma/cpi/version=1
 udma/i2c/version=2